Spexeah/Asuro
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git-svn-id: https://spexeah.com:8443/svn/Asuro@134 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c

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This commit is contained in:
aaron 2017-05-20 12:19:11 +00:00
parent a6325d5062
commit 25ac17e78c
1 changed files with 49 additions and 2 deletions
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51
src/drivers/AHCI.pas
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@ -18,6 +18,8 @@
type type
//Struct hell
TFIS_Type = ( TFIS_Type = (
REG_H2D, REG_D2H, REG_H2D, REG_D2H,
DMA_ACT, DMA_SETUP, DMA_ACT, DMA_SETUP,
@ -26,7 +28,7 @@
); );
TFIS_REG_H2D bitpacked record TFIS_REG_H2D bitpacked record
fis_type : uint8; fis_type : uint8;
port_mult : UBit4; port_mult : UBit4;
rsv0 : UBit3; rsv0 : UBit3;
coc : boolean; coc : boolean;
@ -45,7 +47,52 @@
icc : uint8; icc : uint8;
control : uint8; control : uint8;
rsvl : uint32; rsvl : uint32;
end; end;
TFIS_REG_D2H bitpacked record
fis_type : uint8;
port_mult : UBit4;
rsv0 : UBit2;
i : boolean;
rsvl : boolean;
status : uint8;
error : uint8;
lba0 : uint8;
lba1 : uint8;
lba2 : uint8;
device : uint8;
lba3 : uint8;
lba4 : uint8;
lba5 : uint8;
rsv2 : uint8;
count_low : uint8;
count_high : uint8;
rsv3 : uint16;
rsv4 : uint32;
end;
TFIS_Data bitpacked record
fis_type : uint8;
port_mult : UBit4;
rsv0 : UBit4;
rsv1 : uint16;
data : ^uint32;
end;
TFIS_PIO_Setup bitpakced record
end;
TFIS_DMA_Setup bitpacked record
end;
THBA_Memory bitpacked record
end;
THBA_Port bitpacked record
end;
THBA_FIS bitpacked record
end;
var var