git-svn-id: https://spexeah.com:8443/svn/Asuro@357 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c
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aaron
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@ -1,536 +0,0 @@
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{ ************************************************
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* Asuro
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* Unit: Drivers/AHCI
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* Description: AHCI SATA Driver
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************************************************
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* Author: Aaron Hance
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* Contributors:
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************************************************ }
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unit AHCI;
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interface
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uses
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util,
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PCI,
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drivertypes,
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drivermanagement,
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lmemorymanager,
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console,
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vmemorymanager;
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type
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//Struct hell
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TFIS_Type = (
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REG_H2D = $27,
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REG_D2H = $34,
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DMA_ACT = $39,
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DMA_SETUP = $41,
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DATA = $46,
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BIST = $58,
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PIO_SETUP = $5F,
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DEV_BITS = $A0
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);
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PFIS_REG_H2D = ^TFIS_REG_H2D;
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TFIS_REG_H2D = bitpacked record
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fis_type : uint8;
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port_mult : UBit4;
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rsv0 : UBit3;
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coc : boolean;
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command : uint8;
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feature_low : uint8;
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lba0 : uint8;
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lba1 : uint8;
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lba2 : uint8;
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device : uint8;
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lba3 : uint8;
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lba4 : uint8;
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lba5 : uint8;
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feature_high : uint8;
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count_low : uint8;
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count_high : uint8;
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icc : uint8;
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control : uint8;
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rsvl : uint32;
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end;
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TFIS_REG_D2H = bitpacked record
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fis_type : uint8;
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port_mult : UBit4;
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rsv0 : UBit2;
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i : boolean;
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rsvl : boolean;
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status : uint8;
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error : uint8;
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lba0 : uint8;
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lba1 : uint8;
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lba2 : uint8;
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device : uint8;
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lba3 : uint8;
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lba4 : uint8;
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lba5 : uint8;
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rsv2 : uint8;
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count_low : uint8;
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count_high : uint8;
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rsv3 : uint16;
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rsv4 : uint32;
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end;
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TFIS_Data = bitpacked record
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fis_type : uint8;
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port_mult : UBit4;
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rsv0 : UBit4;
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rsv1 : uint16;
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data : ^uint32;
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end;
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TFIS_PIO_Setup = bitpacked record
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fis_type : uint8;
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pmport : UBit4;
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rsv0 : boolean;
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d : boolean;
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i : boolean;
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rsv1 : boolean;
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status : uint8;
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error : uint8;
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lba0 : uint8;
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lba1 : uint8;
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lba2 : uint8;
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device : uint8;
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lba3 : uint8;
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lba4 : uint8;
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lba5 : uint8;
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rsv2 : uint8;
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countl : uint8;
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counth : uint8;
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rsv3 : uint8;
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e_status : uint8;
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tc : uint16;
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rsv4 : uint16;
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end;
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// TFIS_DMA_Setup = bitpacked record
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// end;
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// THBA_Memory = bitpacked record
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// end;
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// THBA_Port = bitpacked record
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// end;
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// THBA_FIS = bitpacked record
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// end;
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PHBA_PORT = ^THBA_PORT;
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THBA_PORT = bitpacked record
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clb : uint32;
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clbu : uint32;
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fb : uint32;
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fbu : uint32;
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istat : uint32;
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ie : uint32;
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cmd : uint32;
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rsv0 : uint32;
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tfd : uint32;
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sig : uint32;
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ssts : uint32;
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sctl : uint32;
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serr : uint32;
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sact : uint32;
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ci : uint32;
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sntf : uint32;
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fbs : uint32;
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rsv1 : array[0..11] of uint32;
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vendor : array[0..4] of uint32;
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end;
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THBA_MEM = bitpacked record
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cap : uint32; //0
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global_host_control : uint32; //4
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interrupt_status : uint32; //8
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port_implemented : uint32; //c
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version : uint32; //10
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ccc_control : uint32; //14
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ccc_ports : uint32; //18
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em_location : uint32; //1c
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em_Control : uint32; //20
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hcap2 : uint32; //24
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bohc : uint32; //28
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rsv0 : array[0..210] of boolean;
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ports : array[0..31] of THBA_Port;
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end;
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THBAptr = ^THBA_MEM;
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PCMDHeader = ^ TCommand_Header;
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TCommand_Header = bitpacked record
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cfl : ubit5;
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a : boolean;
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w : boolean;
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p : boolean;
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r : boolean;
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b : boolean;
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c : boolean;
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rsv0 : boolean;
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pmp : ubit4;
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PRDTL : uint16;
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PRDTBC : uint32;
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CTBA : uint32;
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CTBAU : uint32;
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rsv1 : array[0..3] of uint32;
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end;
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TPRD_Entry = bitpacked record
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data_base_address : uint32;
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data_bade_address_U : uint32;
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rsv0 : uint32;
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data_byte_count : ubit22;
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rsv1 : ubit9;
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interrupt_oc : boolean;
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end;
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PCommand_Table = ^TCommand_Table;
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TCommand_Table = bitpacked record
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cfis : array[0..64] of uint8;
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acmd : array[0..16] of uint8;
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rsv : array[0..48] of uint8;
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prdt : array[0..7] of TPRD_Entry;
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end;
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var
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//constants
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//SATA_SIG_ATA := $101;
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//SATA_SIG_ATAPI := $EB140101;
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//STA_SIG_SEMB := $C33C0101;
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//STAT_SIG_PM := $96690101;
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AHCI_BASE: uint32 = $400000;
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//other
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ahciController : PuInt32;
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hba : THBAptr;
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sataStorageDevices : array[0..31] of PuInt32;
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sataStorageDeviceCount : uint8;
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procedure init();
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procedure check_ports();
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procedure enable_cmd(port : uint8);
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procedure disable_cmd(port : uint8);
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procedure port_rebase(port : uint8);
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function load(ptr:void): boolean;
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function read(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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function write(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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function find_cmd_slot(port : uint8) : uint32;
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implementation
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procedure init();
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var
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devID : TDeviceIdentifier;
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begin
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console.writestringln('AHCI: STARTING INIT');
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devID.bus:= biPCI;
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devID.id0:= idANY;
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devID.id1:= $00000001;
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devID.id2:= $00000006;
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devID.id3:= $00000001;
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devID.ex:= nil;
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drivermanagement.register_driver('AHCI Controller', @devID, @load);
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end;
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function load(ptr : void) : boolean;
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begin
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ahciController := ptr;
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hba := THBAptr(PPCI_Device(ahciController)^.address5);
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new_page_at_address(uint32(hba));
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AHCI_BASE := PPCI_Device(ahciController)^.address5;
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check_ports();
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load:= true;
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exit;
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end;
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procedure check_ports();
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var
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d : uint32;
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i : uint32;
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activePorts : array[0..32] of uint32;
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begin
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d:= 1;
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for i:= 0 to 31 do begin
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if (d > 0) and (hba^.port_implemented <> 0) then begin // port connected
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if hba^.ports[i].ssts = 259 then begin // port in use and active
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if hba^.ports[i].sig = 1 then begin //device is sata
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sataStorageDevices[sataStorageDeviceCount - 1] := @hba^.ports[i];
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sataStorageDeviceCount += 1;
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port_rebase(i);
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end;
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//TODO implement other types
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end;
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end;
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d := d shl 1;
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end;
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end;
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procedure enable_cmd(port : uint8);
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begin
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while (hba^.ports[port].cmd and $8000) <> 0 do begin end;
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hba^.ports[port].cmd := hba^.ports[port].cmd or $0010;
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hba^.ports[port].cmd := hba^.ports[port].cmd or $0001;
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end;
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procedure disable_cmd(port : uint8);
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begin
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hba^.ports[port].cmd := hba^.ports[port].cmd and $0001;
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while (hba^.ports[port].cmd and $4000) <> 0 do begin end;
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hba^.ports[port].cmd := hba^.ports[port].cmd and $0010;
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end;
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procedure port_rebase(port : uint8);
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var
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cmdHeader : PCMDHeader;
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i : uint16;
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begin
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disable_cmd(port);
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hba^.ports[port].clb := AHCI_BASE + (port shl 10);
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hba^.ports[port].clbu := 0;
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memset(hba^.ports[port].clb, 0, 1024);
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hba^.ports[port].fb := AHCI_BASE + (32 shl 10) + (port shl 8);
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hba^.ports[port].fbu := 0;
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memset(hba^.ports[port].fb, 0, 256);
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cmdheader := PCMDHeader(hba^.ports[port].clb);
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for i:= 0 to 31 do begin
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cmdHeader[i].PRDTL := 8; // no of prdt entries per cmd table
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cmdheader[i].ctba := AHCI_BASE + (40 shl 10) + (port shl 13) + (i shl 8);
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cmdheader[i].CTBAU := 0;
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memset(cmdheader[i].ctba, 0, 256);
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end;
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enable_cmd(port);
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end;
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function read(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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var
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pport : PHBA_PORT;
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slot : uint32;
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cmdHeader : PCMDHeader;
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cmdTable : PCommand_Table;
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cmdFis : PFIS_REG_H2D;
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i : uint32;
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spin : uint32 = 0;
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begin
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console.writestringln('1');
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pport := @hba^.ports[port];
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new_page_at_address(uint32(pport));
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pport^.istat := $ffff;
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slot := find_cmd_slot(port);
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if slot = -1 then exit(false);
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console.writestringln('2');
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cmdHeader := @pport^.clb;
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new_page_at_address(uint32(cmdHeader));
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cmdHeader += slot;
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cmdHeader^.w := false;
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cmdHeader^.PRDTL := uint16(((count - 1) shr 4) + 1);
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console.writestringln('3');
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cmdTable := @cmdheader^.ctba;
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new_page_at_address(uint32(cmdTable));
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memset(uint32(cmdTable), 0, sizeof(TCommand_Table) + (cmdheader^.PRDTL-1) * sizeof(TPRD_Entry));
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console.writestringln('4');
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if cmdHeader^.PRDTL > 0 then begin
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for i:= 0 to cmdHeader^.PRDTL -1 do begin
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cmdTable^.prdt[i].data_base_address := uint32(buf);
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cmdTable^.prdt[i].data_byte_count := 8*1024-1;
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cmdTable^.prdt[i].interrupt_oc := true;
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buf += 4*1024;
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count -= 16;
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end;
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end;
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console.writestringln('5');
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cmdTable^.prdt[i].data_base_address := uint32(buf);
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cmdTable^.prdt[i].data_byte_count := (count shl 9)-1;
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cmdTable^.prdt[i].interrupt_oc := true;
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console.writestringln('6');
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//setup command
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cmdfis := @cmdTable^.cfis;
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new_page_at_address(uint32(cmdfis));
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cmdfis^.coc := true;
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cmdfis^.command := $25;
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cmdfis^.lba0 := uint8(startl);
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cmdfis^.lba1 := uint8(startl shr 8);
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cmdfis^.lba2 := uint8(startl shr 16);
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cmdfis^.device := 1 shl 6;
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cmdfis^.lba3 := uint8(startl shr 24);
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cmdfis^.lba4 := uint8(starth);
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cmdfis^.lba3 := uint8(starth shr 8);
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cmdfis^.count_low := count and $FF;
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cmdfis^.count_high:= (count shr 8) and $FF;
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console.writestringln('7');
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while (pport^.tfd and $88) and spin < 1000000 do begin
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spin += 1;
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end;
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console.writestringln('8');
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if spin = 1000000 then begin
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console.writestringln('AHCI controller: port is hung!');
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read:= false;
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exit;
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end;
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console.writestringln('9');
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pport^.ci := 1 shl slot;
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console.writestringln('10');
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while true do begin
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if(pport^.ci and (1 shl slot)) = (1 shl slot) then break;
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if(pport^.istat and (1 shl 30)) = (1 shl 30) then begin
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console.writestringln('AHCI controller: Disk read error!');
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read:= false;
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exit;
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end;
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end;
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console.writestringln('11');
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if(pport^.istat and (1 shl 30)) = (1 shl 30) then begin
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console.writestringln('AHCI controller: Disk read error!');
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read:= false;
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exit;
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end;
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console.writestringln('12');
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read:= true;
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exit;
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end;
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function write(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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var
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pport : PHBA_PORT;
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slot : uint32;
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cmdHeader : PCMDHeader;
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cmdTable : PCommand_Table;
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cmdFis : PFIS_REG_H2D;
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i : uint32;
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spin : uint32 = 0;
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begin
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console.writestringln('1');
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pport := @hba^.ports[port];
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new_page_at_address(uint32(pport));
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pport^.istat := $ffff;
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slot := find_cmd_slot(port);
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if slot = -1 then exit(false);
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console.writestringln('2');
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cmdHeader := @pport^.clb;
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new_page_at_address(uint32(cmdHeader));
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cmdHeader += slot;
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cmdHeader^.w := false;
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cmdHeader^.PRDTL := uint16(((count - 1) shr 4) + 1);
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console.writestringln('3');
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cmdTable := @cmdheader^.ctba;
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new_page_at_address(uint32(cmdTable));
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new_page_at_address(uint32(@cmdTable^.prdt));
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memset(uint32(cmdTable), 0, sizeof(TCommand_Table) + (cmdheader^.PRDTL-1) * sizeof(TPRD_Entry));
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console.writestringln('4');
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console.writestring('PRDTL: ');
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console.writeintln(cmdHeader^.PRDTL);
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if cmdHeader^.PRDTL > 0 then begin
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for i:= 0 to cmdHeader^.PRDTL -1 do begin
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cmdTable^.prdt[i].data_base_address := uint32(buf);
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cmdTable^.prdt[i].data_byte_count := 8*1024-1;
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cmdTable^.prdt[i].interrupt_oc := true;
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buf += 4*1024;
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count -= 16;
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end;
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end;
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console.writestringln('5');
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cmdTable^.prdt[i].data_base_address := uint32(buf);
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console.writestringln('5.1');
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cmdTable^.prdt[i].data_byte_count := (count shl 9)-1;
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console.writestringln('5.2');
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cmdTable^.prdt[i].interrupt_oc := true;
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console.writestringln('6');
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cmdfis := @cmdTable^.cfis;
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new_page_at_address(uint32(cmdfis));
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cmdfis^.coc := true;
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cmdfis^.command := $35;
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cmdfis^.lba0 := uint8(startl);
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cmdfis^.lba1 := uint8(startl shr 8);
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cmdfis^.lba2 := uint8(startl shr 16);
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cmdfis^.device := 1 shl 6;
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cmdfis^.lba3 := uint8(startl shr 24);
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cmdfis^.lba4 := uint8(starth);
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cmdfis^.lba3 := uint8(starth shr 8);
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cmdfis^.count_low := count and $FF;
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cmdfis^.count_high:= (count shr 8) and $FF;
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console.writestringln('7');
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while (pport^.tfd and $88) and spin < 1000000 do begin
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spin += 1;
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end;
|
||||
|
||||
console.writestringln('8');
|
||||
if spin = 1000000 then begin
|
||||
console.writestringln('AHCI controller: port is hung!');
|
||||
write:= false;
|
||||
exit;
|
||||
end;
|
||||
|
||||
console.writestringln('9');
|
||||
pport^.ci := 1 shl slot;
|
||||
|
||||
console.writestringln('10');
|
||||
while true do begin
|
||||
if(pport^.ci and (1 shl slot)) = (1 shl slot) then break;
|
||||
if(pport^.istat and (1 shl 30)) = (1 shl 30) then begin
|
||||
console.writestringln('AHCI controller: Disk write error!');
|
||||
write:= false;
|
||||
exit;
|
||||
end;
|
||||
end;
|
||||
|
||||
console.writestringln('11');
|
||||
if(pport^.istat and (1 shl 30)) = (1 shl 30) then begin
|
||||
console.writestringln('AHCI controller: Disk write error!');
|
||||
write:= false;
|
||||
exit;
|
||||
end;
|
||||
|
||||
console.writestringln('12');
|
||||
write:= true;
|
||||
exit;
|
||||
end;
|
||||
|
||||
function find_cmd_slot(port : uint8) : uint32;
|
||||
var
|
||||
slots : uint32;
|
||||
i : uint32;
|
||||
begin
|
||||
slots := hba^.ports[port].sact or hba^.ports[port].ci;
|
||||
for i:=0 to 31 do begin
|
||||
if (slots and 1) = 0 then begin
|
||||
exit(i);
|
||||
end;
|
||||
slots := slots shr 1;
|
||||
end;
|
||||
console.writestringln('AHCI Controller: Unable to find free command slots!');
|
||||
exit(-1);
|
||||
end;
|
||||
|
||||
end.
|
||||
|
||||
@ -1,271 +0,0 @@
|
||||
{ ************************************************
|
||||
* Asuro
|
||||
* Unit: Drivers/ATA
|
||||
* Description: ATA DMA Driver
|
||||
* currently a hack needs to be re-written if works
|
||||
************************************************
|
||||
* Author: Aaron Hance
|
||||
* Contributors:
|
||||
************************************************ }
|
||||
unit ATA;
|
||||
|
||||
interface
|
||||
|
||||
uses
|
||||
util,
|
||||
drivertypes,
|
||||
console,
|
||||
terminal,
|
||||
isr76,
|
||||
vmemorymanager;
|
||||
|
||||
type
|
||||
|
||||
intptr = ^uint32;
|
||||
|
||||
ATA_Device = record
|
||||
reading : boolean;
|
||||
master : boolean;
|
||||
primary : boolean;
|
||||
currentIndex : uint16;
|
||||
device_lba : uint32;
|
||||
Command_Register : uint32;
|
||||
Status_Register : uint32;
|
||||
PRDT_Address_Reg : uint32;
|
||||
end;
|
||||
|
||||
Physical_Region_Descriptor = bitpacked record
|
||||
empty0 : 0..1;
|
||||
MRPB_Address : 1..32; // memory address
|
||||
Byte_Count : 32..47; // size in bytes (0 is 64K)
|
||||
empty1 : 47..63;
|
||||
EOT : 63..64; // end of table
|
||||
empty2 : 64..65;
|
||||
end;
|
||||
|
||||
ATA_Command_Buffer = bitpacked record
|
||||
start_stop_bit : 0..1; // 0 stopped
|
||||
read_write_bit : 3..4; // 0 read
|
||||
end;
|
||||
|
||||
ATA_Status_Buffer = bitpacked record end;
|
||||
|
||||
ATA_IO_PORT = record
|
||||
data : uint16;
|
||||
error : uint8;
|
||||
sector_count : uint8;
|
||||
lba_low : uint8;
|
||||
lba_mid : uint8;
|
||||
lba_hi : uint8;
|
||||
drive : uint8;
|
||||
command : uint8;
|
||||
end;
|
||||
|
||||
var
|
||||
ports : ATA_IO_PORT;
|
||||
devices : array[0..4] of ATA_Device;
|
||||
PRD_Table : array[0..100] of Physical_Region_Descriptor; // up 64K r/w each, upto 8000 supported per table.
|
||||
controller : TPCI_device;
|
||||
|
||||
procedure init(_controller : TPCI_device);
|
||||
procedure read(address : uint32; data_lba : uint32; data_bytes : uint32);
|
||||
procedure write(address : uint32; data_lba : uint32; data_bytes : uint32);
|
||||
procedure callback(data : void);
|
||||
|
||||
implementation
|
||||
|
||||
procedure init(_controller : TPCI_device); //alloc, pmem; map_page vmem;
|
||||
begin
|
||||
console.writestringln('ATA: INIT BEGIN.');
|
||||
isr76.hook(uint32(@callback));
|
||||
|
||||
controller := _controller;
|
||||
|
||||
new_page_at_address(controller.address4);
|
||||
|
||||
devices[0].primary := true;
|
||||
devices[0].Command_Register := controller.address4;
|
||||
devices[0].Status_Register := controller.address4 + 2;
|
||||
devices[0].PRDT_Address_Reg := controller.address4 + 4;
|
||||
|
||||
ports.command := $1F7;
|
||||
ports.lba_low := $1F3;
|
||||
ports.lba_mid := $1F4;
|
||||
ports.lba_hi := $1F5;
|
||||
ports.drive := $1F6;
|
||||
ports.sector_count := $F2;
|
||||
console.writestringln('ATA: INIT END.');
|
||||
end;
|
||||
|
||||
procedure read(address : uint32; data_lba : uint32; data_bytes : uint32);
|
||||
var
|
||||
PRD : Physical_Region_Descriptor;
|
||||
empty_table : array[0..100] of Physical_Region_Descriptor;
|
||||
i : uint32;
|
||||
ptr : intptr;
|
||||
sector_count : uint8;
|
||||
cb : ATA_Command_Buffer;
|
||||
begin
|
||||
devices[0].device_lba := data_lba;
|
||||
devices[0].reading := true;
|
||||
PRD_Table := empty_table;
|
||||
PRD.MRPB_Address := address;
|
||||
|
||||
//limit
|
||||
if data_bytes > 6400000 then exit;
|
||||
|
||||
if data_bytes < 64001 then begin
|
||||
PRD.EOT := 1;
|
||||
if data_bytes = 64000 then begin
|
||||
PRD.Byte_Count := 0
|
||||
end else begin
|
||||
PRD.Byte_Count := data_bytes;
|
||||
end;
|
||||
end else begin
|
||||
while data_bytes > 64000 do begin
|
||||
PRD.EOT := 0;
|
||||
PRD.MRPB_Address := address;
|
||||
PRD.Byte_Count := 0;
|
||||
|
||||
data_bytes := data_bytes - 64000;
|
||||
address := address + 64000;
|
||||
end;
|
||||
|
||||
PRD.EOT := 1;
|
||||
PRD.MRPB_Address := address;
|
||||
PRD.Byte_Count := data_bytes;
|
||||
|
||||
end;
|
||||
|
||||
ptr := intptr(devices[0].PRDT_Address_Reg);
|
||||
ptr^ := uint32(@PRD_Table);
|
||||
|
||||
ptr := intptr(devices[0].Status_Register);
|
||||
ptr^ := 0;
|
||||
|
||||
outb(ports.drive, $A0);
|
||||
outb(ports.sector_count, 125);
|
||||
outb(ports.lba_low, (data_lba and $000000FF));
|
||||
outb(ports.lba_mid, (data_lba and $0000FF00) SHR 8);
|
||||
outb(ports.lba_hi, (data_lba and $0000FF00) SHR 16);
|
||||
outb(ports.command, $C8);
|
||||
devices[0].currentIndex := 1;
|
||||
|
||||
cb.start_stop_bit := 1;
|
||||
cb.read_write_bit := 0;
|
||||
|
||||
ptr := intptr(devices[0].Command_Register);
|
||||
ptr^ := uint8(cb);
|
||||
|
||||
end;
|
||||
|
||||
procedure write(address : uint32; data_lba : uint32; data_bytes : uint32);
|
||||
var
|
||||
PRD : Physical_Region_Descriptor;
|
||||
empty_table : array[0..100] of Physical_Region_Descriptor;
|
||||
i : uint32;
|
||||
ptr : intptr;
|
||||
sector_count : uint8;
|
||||
cb : ATA_Command_Buffer;
|
||||
begin
|
||||
devices[0].device_lba := data_lba;
|
||||
devices[0].reading := true;
|
||||
PRD_Table := empty_table;
|
||||
PRD.MRPB_Address := address;
|
||||
|
||||
//limit
|
||||
if data_bytes > 6400000 then exit;
|
||||
|
||||
if data_bytes < 64001 then begin
|
||||
PRD.EOT := 1;
|
||||
if data_bytes = 64000 then begin
|
||||
PRD.Byte_Count := 0
|
||||
end else begin
|
||||
PRD.Byte_Count := data_bytes;
|
||||
end;
|
||||
end else begin
|
||||
while data_bytes > 64000 do begin
|
||||
PRD.EOT := 0;
|
||||
PRD.MRPB_Address := address;
|
||||
PRD.Byte_Count := 0;
|
||||
|
||||
data_bytes := data_bytes - 64000;
|
||||
address := address + 64000;
|
||||
end;
|
||||
|
||||
PRD.EOT := 1;
|
||||
PRD.MRPB_Address := address;
|
||||
PRD.Byte_Count := data_bytes;
|
||||
|
||||
end;
|
||||
|
||||
ptr := intptr(devices[0].PRDT_Address_Reg);
|
||||
ptr^ := uint32(@PRD_Table);
|
||||
|
||||
ptr := intptr(devices[0].Status_Register);
|
||||
ptr^ := 0;
|
||||
|
||||
outb(ports.drive, $A0);
|
||||
outb(ports.sector_count, 125);
|
||||
outb(ports.lba_low, (data_lba and $000000FF));
|
||||
outb(ports.lba_mid, (data_lba and $0000FF00) SHR 8);
|
||||
outb(ports.lba_hi, (data_lba and $0000FF00) SHR 16);
|
||||
outb(ports.command, $CA);
|
||||
devices[0].currentIndex := 1;
|
||||
|
||||
cb.start_stop_bit := 1;
|
||||
cb.read_write_bit := 1;
|
||||
|
||||
ptr := intptr(devices[0].Command_Register);
|
||||
ptr^ := uint8(cb);
|
||||
|
||||
end;
|
||||
|
||||
procedure callback(data : void); //need r/w, is last
|
||||
var
|
||||
cb : ATA_Command_Buffer;
|
||||
ptr : intptr;
|
||||
tmp : uint16;
|
||||
mode : uint8;
|
||||
begin
|
||||
if(PRD_Table[devices[0].currentIndex - 1].EOT = 1) then begin
|
||||
//other stuff
|
||||
exit;
|
||||
end;
|
||||
|
||||
//if(devices[0].reading = true) then begin
|
||||
if(PRD_Table[devices[0].currentIndex].EOT = 0) then begin
|
||||
outb(ports.sector_count, 125);
|
||||
outb(ports.lba_low, (devices[0].device_lba + (64000 * devices[0].currentIndex)) and $000000FF);
|
||||
outb(ports.lba_mid, (((devices[0].device_lba + (64000 * devices[0].currentIndex))) and $0000FF00) SHR 8);
|
||||
outb(ports.lba_hi, (((devices[0].device_lba + (64000 * devices[0].currentIndex))) and $0000FF00) SHR 16);
|
||||
//outb(ports.command, $C8);
|
||||
end else begin
|
||||
tmp := uint16((PRD_Table[devices[0].currentIndex].Byte_Count and $FFFF) DIV 512);
|
||||
outb(ports.sector_count, uint16(tmp)); // wont work if 64k
|
||||
outb(ports.lba_low, (devices[0].device_lba + (64000 * devices[0].currentIndex)) and $000000FF);
|
||||
outb(ports.lba_mid, (((devices[0].device_lba + (64000 * devices[0].currentIndex))) and $0000FF00) SHR 8);
|
||||
outb(ports.lba_hi, (((devices[0].device_lba + (64000 * devices[0].currentIndex))) and $0000FF00) SHR 16);
|
||||
//outb(ports.command, $C8);
|
||||
end;
|
||||
|
||||
if(devices[0].reading = true) then begin
|
||||
outb(ports.command, $C8);
|
||||
cb.start_stop_bit := 1;
|
||||
cb.read_write_bit := 0;
|
||||
end else begin
|
||||
outb(ports.command, $CA);
|
||||
cb.start_stop_bit := 1;
|
||||
cb.read_write_bit := 1;
|
||||
end;
|
||||
ptr := intptr(devices[0].Command_Register);
|
||||
ptr^ := uint8(cb);
|
||||
|
||||
|
||||
devices[0].currentIndex := devices[0].currentIndex + 1;
|
||||
//end;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
end.
|
||||
Loading…
x
Reference in New Issue
Block a user