Spexeah/Asuro
3
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

updates and stuff

Browse Source 
git-svn-id: https://spexeah.com:8443/svn/Asuro@1442 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c
This commit is contained in:
kieron
2020-07-21 23:50:07 +00:00
parent 99fc00450e
commit 9820ab7756
3 changed files with 9 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/isr/isr_types.pas
View File

@ -20,10 +20,10 @@ type
EDX : uint32;
ESI : uint32;
EDI : uint32;
DS : uint32;
ES : uint32;
FS : uint32;
GS : uint32;
DS : uint16;
ES : uint16;
FS : uint16;
GS : uint16;
end;
PInterruptRegisters = ^TInterruptRegisters;
@ -63,10 +63,10 @@ procedure correctInterruptRegisters(Errorcode : boolean);
begin
if IntReg <> nil then begin
If errorcode then begin
IntSpec:= PInterruptSpecialRegisters(uint32(IntReg) + uint32(SizeOf(TInterruptRegisters)) + uint32(Sizeof(TError)));
IntErr:= PError(uint32(IntReg) + uint32(sizeof(TInterruptRegisters)));
IntSpec:= PInterruptSpecialRegisters(uint32(IntReg) + sizeof(TInterruptRegisters) + uint32(4));
IntErr:= PError(uint32(IntReg) + sizeof(TInterruptRegisters));
end else begin
IntSpec:= PInterruptSpecialRegisters(uint32(IntReg) + uint32(SizeOf(TInterruptRegisters)));
IntSpec:= PInterruptSpecialRegisters(uint32(IntReg) + sizeof(TInterruptRegisters));
IntErr:= PError(@ZeroError);
end;
end;

3
src/isr/isrmanager.pas
View File

@ -76,7 +76,8 @@ end;
procedure ISR_3; interrupt;
begin
asm
MOV IntReg, EBP end;
MOV IntReg, EBP
end;
ISR_N(3);
end;