Cleanup
This commit is contained in:
parent
babe4290e4
commit
a2f6d7e76d
@ -50,6 +50,7 @@ function send_read_dma(device : PAHCI_Device; lba : uint64; count : uint32; buff
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function send_write_dma(device : PAHCI_Device; lba : uint64; count : uint32; buffer : puint32) : boolean;
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function read_atapi(device : PAHCI_Device; lba : uint64; count : uint32; buffer : puint32) : boolean;
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implementation
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procedure init();
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@ -113,8 +114,44 @@ begin
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// Clear the SERR register by writing 1s to it.
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port^.sata_error := $FFFFFFFF;
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start_port(port);
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end;
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// procedure reset_port(port : PHBA_Port);
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// var
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// ssts, serr, timeout : uint32;
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// begin
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// console.writestringln('AHCI: Performing a full port reset.');
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// port^.cmd := port^.cmd and not $1;
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// // Wait until CR (bit 15) is cleared.
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// timeout := 0;
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// while (port^.cmd and $8000) <> 0 do begin
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// timeout := timeout + 1;
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// if timeout > 1000000 then begin
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// console.writestringln('AHCI: Port reset timeout.');
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// break;
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// end;
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// end;
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// port^.sata_ctrl := port^.sata_ctrl and $FFFF0000;
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// port^.sata_ctrl := port^.sata_ctrl or $1;
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// psleep(10);
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// port^.sata_ctrl := port^.sata_ctrl and $FFFF0000;
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// while (port^.sata_status and $F) <> $3 do begin
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// //wait for the port to be ready
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// end;
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// // Clear the SERR register by writing 1s to it.
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// port^.sata_error := $FFFFFFFF;
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// // start_port(port);
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// end;
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{
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Check the ports on the controller and setup the command list, FIS, and command table
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}
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@ -229,7 +266,6 @@ begin
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//reset the port
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reset_port(port);
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start_port(port);
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//print sata status
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console.writestring('AHCI: sata status: ');
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@ -383,19 +419,23 @@ begin
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console.writestringln('');
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buffer := puint32(kalloc(512));
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memset(uint32(buffer), 0, 512);
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buffer := puint32(kalloc(2048));
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memset(uint32(buffer), 0, 2048);
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//send a read DMA command to the device
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if isATAPI then begin
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read_atapi(device, 16, 512, buffer);
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read_atapi(device, 0, 2048, buffer);
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end else begin
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send_read_dma(device, 10, 512, buffer);
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memset(uint32(buffer), $77, 2048);
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send_write_dma(device, 22, 512, buffer);
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memset(uint32(buffer), 0, 2048);
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send_read_dma(device, 22, 512, buffer);
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end;
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//print the buffer
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for i:=0 to 63 do begin
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console.writehex(uint32(buffer[i]));
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console.writehex(puInt8(buffer)[i]);
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console.writestring(' ');
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end;
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console.writestringln('');
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@ -536,7 +576,6 @@ begin
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console.writestringln('AHCI: Sending read DMA command');
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reset_port(device^.port);
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start_port(device^.port);
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//prdt count is 22 bits
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prdt_count := (count div 4194304) + 1;
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@ -647,7 +686,6 @@ begin
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console.writestringln('AHCI: Sending write DMA command');
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reset_port(device^.port);
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start_port(device^.port);
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//prdt count is 22 bits
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prdt_count := (count div 4194304) + 1;
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@ -688,6 +726,8 @@ begin
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fis^.command := ATA_CMD_WRITE_DMA_EXT;
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fis^.device := $40; // LBA mode 48?
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count:= count div 512;
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fis^.lba0 := lba and $FF;
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fis^.lba1 := (
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lba shr 8) and $FF;
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@ -764,7 +804,6 @@ begin
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console.writestringln('AHCI: Sending read ATAPI command');
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reset_port(device^.port);
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start_port(device^.port);
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//prdt count is 22 bits
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prdt_count := (count div 4194304) + 1;
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@ -781,12 +820,13 @@ begin
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cmd_header^.wrt := 0;
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cmd_header^.prdtl := 1;
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cmd_header^.atapi := 1;
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cmd_header^.clear_busy := 1;
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// Setup the command table (using slot 0)
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cmd_table := PHBA_CMD_TABLE(uint32(device^.command_table) + (slot * sizeof(THBA_CMD_TABLE)));
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cmd_table^.prdt[0].dba := vtop(uint32(buffer));
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cmd_table^.prdt[0].dbc := 512 - 1; // 512 bytes (0-based count
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cmd_table^.prdt[0].dbc := 2048 - 1; // 512 bytes (0-based count
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cmd_table^.prdt[0].int := 1; // Interrupt on completion
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// Construct the Command FIS in the command table's CFIS area
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@ -795,7 +835,7 @@ begin
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fis^.fis_type := uint8(FIS_TYPE_REG_H2D);
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fis^.c := $1;
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fis^.command := ATA_CMD_PACKET;
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fis^.device := $A0; // LBA mode 48?
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fis^.device := $A0;
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fis^.featurel := fis^.featurel or 1; //setting both of these might not work on real hardware
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fis^.featurel := fis^.featurel or (1 shl 2);
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@ -1,296 +0,0 @@
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// // Copyright 2021 Aaron Hance
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// //
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// // Licensed under the Apache License, Version 2.0 (the "License");
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// // you may not use this file except in compliance with the License.
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// // You may obtain a copy of the License at
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// //
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// // http://www.apache.org/licenses/LICENSE-2.0
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// //
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// // Unless required by applicable law or agreed to in writing, software
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// // distributed under the License is distributed on an "AS IS" BASIS,
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// // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// // See the License for the specific language governing permissions and
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// // limitations under the License.
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// {
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// Drivers->Storage->AHCI - AHCI SATA Driver.
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// @author(Aaron Hance <ah@aaronhance.me>)
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// }
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// unit AHCI;
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// interface
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// uses
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// util,
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// PCI,
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// drivertypes,
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// drivermanagement,
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// lmemorymanager,
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// console,
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// vmemorymanager;
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// type
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// //Struct hell
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// TFIS_Type = (
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// REG_H2D = $27,
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// REG_D2H = $34,
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// DMA_ACT = $39,
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// DMA_SETUP = $41,
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// DATA = $46,
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// BIST = $58,
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// PIO_SETUP = $5F,
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// DEV_BITS = $A0
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// );
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// PFIS_REG_H2D = ^TFIS_REG_H2D;
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// TFIS_REG_H2D = bitpacked record
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// fis_type : uint8;
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// port_mult : UBit4;
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// rsv0 : UBit3;
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// coc : boolean;
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// command : uint8;
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// feature_low : uint8;
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// lba0 : uint8;
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// lba1 : uint8;
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// lba2 : uint8;
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// device : uint8;
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// lba3 : uint8;
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// lba4 : uint8;
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// lba5 : uint8;
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// feature_high : uint8;
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// count_low : uint8;
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// count_high : uint8;
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// icc : uint8;
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// control : uint8;
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// rsvl : uint32;
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// end;
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// TFIS_REG_D2H = bitpacked record
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// fis_type : uint8;
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// port_mult : UBit4;
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// rsv0 : UBit2;
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// i : boolean;
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// rsvl : boolean;
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// status : uint8;
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// error : uint8;
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// lba0 : uint8;
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// lba1 : uint8;
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// lba2 : uint8;
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// device : uint8;
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// lba3 : uint8;
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// lba4 : uint8;
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// lba5 : uint8;
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// rsv2 : uint8;
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// count_low : uint8;
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// count_high : uint8;
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// rsv3 : uint16;
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// rsv4 : uint32;
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// end;
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// TFIS_Data = bitpacked record
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// fis_type : uint8;
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// port_mult : UBit4;
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// rsv0 : UBit4;
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// rsv1 : uint16;
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// data : ^uint32;
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// end;
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// TFIS_PIO_Setup = bitpacked record
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// fis_type : uint8;
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// pmport : UBit4;
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// rsv0 : boolean;
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// d : boolean;
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// i : boolean;
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// rsv1 : boolean;
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// status : uint8;
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// error : uint8;
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// lba0 : uint8;
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// lba1 : uint8;
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// lba2 : uint8;
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// device : uint8;
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// lba3 : uint8;
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// lba4 : uint8;
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// lba5 : uint8;
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// rsv2 : uint8;
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// countl : uint8;
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// counth : uint8;
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// rsv3 : uint8;
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// e_status : uint8;
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// tc : uint16;
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// rsv4 : uint16;
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// end;
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// // TFIS_DMA_Setup = bitpacked record
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// // end;
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// // THBA_Memory = bitpacked record
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// // end;
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// // THBA_Port = bitpacked record
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// // end;
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// // THBA_FIS = bitpacked record
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// // end;
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// PHBA_PORT = ^THBA_PORT;
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// THBA_PORT = bitpacked record
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// clb : uint32;
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// clbu : uint32;
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// fb : uint32;
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// fbu : uint32;
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// istat : uint32;
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// ie : uint32;
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// cmd : uint32;
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// rsv0 : uint32;
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// tfd : uint32;
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// sig : uint32;
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// ssts : uint32;
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// sctl : uint32;
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// serr : uint32;
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// sact : uint32;
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// ci : uint32;
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// sntf : uint32;
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// fbs : uint32;
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// rsv1 : array[0..11] of uint32;
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// vendor : array[0..4] of uint32;
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// end;
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// THBA_MEM = bitpacked record
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// cap : uint32; //0
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// global_host_control : uint32; //4
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// interrupt_status : uint32; //8
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// port_implemented : uint32; //c
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// version : uint32; //10
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// ccc_control : uint32; //14
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// ccc_ports : uint32; //18
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// em_location : uint32; //1c
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// em_Control : uint32; //20
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// hcap2 : uint32; //24
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// bohc : uint32; //28
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// rsv0 : array[0..210] of boolean;
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// ports : array[0..31] of THBA_Port;
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// end;
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// PHBA = ^THBA_MEM;
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// PCMDHeader = ^ TCommand_Header;
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// TCommand_Header = bitpacked record
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// cfl : ubit5;
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// a : boolean;
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// w : boolean;
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// p : boolean;
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// r : boolean;
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// b : boolean;
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// c : boolean;
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// rsv0 : boolean;
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// pmp : ubit4;
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// PRDTL : uint16;
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// PRDTBC : uint32;
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// CTBA : uint32;
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// CTBAU : uint32;
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// rsv1 : array[0..3] of uint32;
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// end;
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// TPRD_Entry = bitpacked record
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// data_base_address : uint32;
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// data_bade_address_U : uint32;
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// rsv0 : uint32;
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// data_byte_count : ubit22;
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// rsv1 : ubit9;
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// interrupt_oc : boolean;
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// end;
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// PCommand_Table = ^TCommand_Table;
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// TCommand_Table = bitpacked record
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// cfis : array[0..64] of uint8;
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// acmd : array[0..16] of uint8;
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// rsv : array[0..48] of uint8;
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// prdt : array[0..7] of TPRD_Entry;
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// end;
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// TSataDevice = record
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// controller : uint8;
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// port : uint8;
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// end;
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// var
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// //constants
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// //SATA_SIG_ATA := $101;
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// //SATA_SIG_ATAPI := $EB140101;
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// //STA_SIG_SEMB := $C33C0101;
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// //STAT_SIG_PM := $96690101;
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// AHCI_BASE: uint32 = $400000; //irrelivent
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// //other
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// ahciControllers : array[0.16] of PuInt32;
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// ahciControllerCount : uint8 = 0;
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// hba : array[0..16] of PHBA;
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// sataDevices : array[0..127] of TSataDevice;
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// sataDeviceCount : uint8;
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// procedure init();
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// procedure check_ports(controller : uint8);
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// procedure enable_cmd(port : uint8);
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// procedure disable_cmd(port : uint8);
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// procedure port_rebase(port : uint8);
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// function load(ptr:void): boolean;
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// function read(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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// function write(port : uint8; startl : uint32; starth : uint32; count : uint32; buf : PuInt32) : boolean;
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// function find_cmd_slot(port : uint8) : uint32;
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// implementation
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// procedure init();
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// var
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// devID : TDeviceIdentifier;
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// begin
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// console.writestringln('AHCI: Registering driver');
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// devID.bus:= biPCI;
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// devID.id0:= idANY;
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// devID.id1:= $00000001;
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// devID.id2:= $00000006;
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// devID.id3:= $00000001;
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// devID.id4:= idANY;
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// devID.ex:= nil;
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// drivermanagement.register_driver('AHCI Driver', @devID, @load);
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// end;
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// procedure load(ptr : void);
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// begin
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// console.writestringln('AHCI: initilizing a new controller');
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// ahciControllers[ahciControllerCount] := ptr;
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// hba[ahciControllerCount] := PPCI_Device(ptr)^.address5;
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// new_page_at_address(hba[ahciControllerCount]);
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// //here would be any controller setup needed
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// check_ports(ahciControllerCount);
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// ahciControllerCount += 1;
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// exit(true);
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// end;
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// procedure check_ports(controller : uint8);
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// var
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// d : uint32 = 1;
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// i : uint32;
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// begin
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// for i:=0 to 31 do begin
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// if (d > 0) and (hba[controller]^.port_implemented shr i) = 1 then begin
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// if (hba[controller]^.ports[i].ssts shr 8) <> 1 and (hba[controller]^.ports[i].ssts and $0F) <> 3 then begin
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// if hba[controller]^.ports[i].sig = 1 then begin
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// //device is sata
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// sataDevices[sataDeviceCount].controller := controller;
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// sataDevices[sataDeviceCount].port := i;
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// sataDeviceCount += 1;
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// end;
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// //TODO implement ATAPI
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// end;
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// end;
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// end;
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// end;
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@ -1,85 +0,0 @@
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// Copyright 2021 Aaron Hance
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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{
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Drivers->Storage->ATA_ISR - Primary ATA IRQ.
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@author(Aaron Hance <ah@aaronhance.me>)
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}
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unit ATA_ISR;
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interface
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uses
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util,
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console,
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isr_types,
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isrmanager,
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IDT;
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procedure register();
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procedure hook(hook_method : uint32);
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procedure unhook(hook_method : uint32);
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implementation
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var
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Hooks : Array[1..MAX_HOOKS] of pp_hook_method;
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procedure Main(); interrupt;
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var
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i : integer;
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begin
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CLI;
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for i:=0 to MAX_HOOKS-1 do begin
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if uint32(Hooks[i]) <> 0 then Hooks[i](void($00000000));
|
||||
end;
|
||||
console.writestringln('Disk Operation Complete');
|
||||
end;
|
||||
|
||||
procedure register();
|
||||
begin
|
||||
memset(uint32(@Hooks[0]), 0, sizeof(pp_hook_method)*MAX_HOOKS);
|
||||
//isrmanager.registerISR(76, @Main);
|
||||
//IDT.set_gate(76, uint32(@Main), $08, ISR_RING_0);
|
||||
end;
|
||||
|
||||
procedure hook(hook_method : uint32);
|
||||
var
|
||||
i : uint32;
|
||||
|
||||
begin
|
||||
for i:=0 to MAX_HOOKS-1 do begin
|
||||
if uint32(Hooks[i]) = hook_method then exit;
|
||||
end;
|
||||
for i:=0 to MAX_HOOKS-1 do begin
|
||||
if uint32(Hooks[i]) = 0 then begin
|
||||
Hooks[i]:= pp_hook_method(hook_method);
|
||||
exit;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure unhook(hook_method : uint32);
|
||||
var
|
||||
i : uint32;
|
||||
begin
|
||||
for i:=0 to MAX_HOOKS-1 do begin
|
||||
If uint32(Hooks[i]) = hook_method then Hooks[i]:= nil;
|
||||
exit;
|
||||
end;
|
||||
end;
|
||||
|
||||
end.
|
||||
@ -15,6 +15,8 @@
|
||||
{
|
||||
Drivers->Storage->ide - IDE Driver.
|
||||
|
||||
NOT FINSIHED NEEDS WORK
|
||||
|
||||
@author(Aaron Hance <ah@aaronhance.me>)
|
||||
}
|
||||
unit ide;
|
||||
|
||||
@ -1,3 +1,27 @@
|
||||
// Copyright 2021 Aaron Hance
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
{
|
||||
Drivers->Storage->ATAPI - ATAPI Driver.
|
||||
|
||||
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
!!!!!!!!!!!!!!!!!!!!!! CURRENTLY NOT FUNCTIONAL !!!!!!!!!!!!!!!!!!!!!!
|
||||
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
|
||||
@author(Aaron Hance <ah@aaronhance.me>)
|
||||
}
|
||||
|
||||
unit atapi;
|
||||
|
||||
interface
|
||||
|
||||
@ -1,504 +0,0 @@
|
||||
{ ************************************************
|
||||
* Asuro
|
||||
* Unit: Drivers/storage/IDE
|
||||
* Description: IDE ATA Driver
|
||||
*
|
||||
************************************************
|
||||
* Author: Aaron Hance
|
||||
* Contributors:
|
||||
************************************************ }
|
||||
unit IDE;
|
||||
|
||||
interface
|
||||
|
||||
uses
|
||||
util,
|
||||
drivertypes,
|
||||
console,
|
||||
terminal,
|
||||
drivermanagement,
|
||||
vmemorymanager,
|
||||
lmemorymanager,
|
||||
storagemanagement,
|
||||
strings,
|
||||
tracer,
|
||||
drivemanager,
|
||||
storagetypes;
|
||||
|
||||
type
|
||||
TPortMode = (P_READ, P_WRITE);
|
||||
|
||||
TIdentResponse = array[0..255] of uint16;
|
||||
|
||||
TIDE_Channel_Registers = record
|
||||
base : uint16;
|
||||
ctrl : uint16;
|
||||
bmide : uint16;
|
||||
noInter : uint8
|
||||
end;
|
||||
|
||||
TIDE_Device = record
|
||||
exists : boolean;
|
||||
isPrimary : boolean;
|
||||
isMaster : boolean;
|
||||
isATAPI : boolean;
|
||||
info : TIdentResponse;
|
||||
end;
|
||||
|
||||
TIDE_Status = bitpacked record
|
||||
Busy : Boolean;
|
||||
Ready : Boolean;
|
||||
Fault : Boolean;
|
||||
Seek : Boolean;
|
||||
DRQ : Boolean;
|
||||
CORR : Boolean;
|
||||
IDDEX : Boolean;
|
||||
ERROR : Boolean;
|
||||
end;
|
||||
PIDE_Status = ^TIDE_Status;
|
||||
|
||||
|
||||
const
|
||||
ATA_SR_BUSY = $80; //BUSY
|
||||
ATA_SR_DRDY = $40; //DRIVE READY
|
||||
ATA_SR_DF = $20; //DRIVE WRITE FAULT
|
||||
ATA_SR_DSC = $10; //DRIVE SEEK COMPLETE
|
||||
ATA_SR_DRQ = $08; //DATA REQUEST READY
|
||||
ATA_SR_CORR = $04; //CORRECTED DATA
|
||||
ATA_SR_IDX = $02; //INLEX
|
||||
ATA_SR_ERR = $01; //ERROR
|
||||
|
||||
ATA_ER_BBK = $80; //BAD SECTOR
|
||||
ATA_ER_UNC = $40; //UNCORRECTABLE DATA
|
||||
ATA_ER_MC = $20; //NO MEDIA
|
||||
ATA_ER_IDNF = $10; //ID MARK NOT FOUND
|
||||
ATA_ER_MCR = $08; //NO MEDIA
|
||||
ATA_ER_ABRT = $04; //COMMAND ABORTED
|
||||
ATA_ER_TK0NF = $02; //TRACK 0 NOT FOUND
|
||||
ATA_ER_AMNF = $01; //NO ADDRESS MARK
|
||||
|
||||
ATA_CMD_READ_PIO = $20;
|
||||
ATA_CMD_READ_PIO_EXT = $24;
|
||||
ATA_CMD_READ_DMA = $C8;
|
||||
ATA_CMD_READ_DMA_EXT = $25;
|
||||
ATA_CMD_WRITE_PIO = $30;
|
||||
ATA_CMD_WRITE_PIO_EXT = $34;
|
||||
ATA_CMD_WRITE_DMA = $CA;
|
||||
ATA_CMD_WRITE_DMA_EXT = $35;
|
||||
ATA_CMD_CACHE_FLUSH = $E7;
|
||||
ATA_CMD_CACHE_FLUSH_EXT = $EA;
|
||||
ATA_CMD_PACKET = $A0;
|
||||
ATA_CMD_IDENTIFY_PACKET = $A1;
|
||||
ATA_CMD_IDENTIFY = $EC;
|
||||
|
||||
ATAPI_CMD_READ = $A8;
|
||||
ATAPI_CMD_EJECT = $1B;
|
||||
|
||||
ATA_IDENT_DEVICETYPE = $0;
|
||||
ATA_IDENT_CYLINDERS = $2;
|
||||
ATA_IDENT_HEADS = $6;
|
||||
ATA_IDENT_SECOTRS = $12;
|
||||
ATA_IDENT_SERIAL = $20;
|
||||
ATA_IDENT_MODEL = $54;
|
||||
ATA_IDENT_CAPABILITIES = $98;
|
||||
ATA_IDENT_FIELDVALID = $106;
|
||||
ATA_IDENT_MAX_LBA = $120;
|
||||
ATA_IDENT_COMMANDSETS = $164;
|
||||
ATA_IDENT_MAX_LBA_EXT = $200;
|
||||
|
||||
ATA_REG_DATA = $00;
|
||||
ATA_REG_ERROR = $01;
|
||||
ATA_REG_FEATURES = $01;
|
||||
ATA_REG_SECCOUNT = $02;
|
||||
ATA_REG_LBA0 = $03;
|
||||
ATA_REG_LBA1 = $04;
|
||||
ATA_REG_LBA2 = $05;
|
||||
ATA_REG_HDDEVSEL = $06;
|
||||
ATA_REG_COMMAND = $07;
|
||||
ATA_REG_STATUS = $07;
|
||||
ATA_REG_SECCOUNT1 = $08;
|
||||
ATA_REG_LBA3 = $09;
|
||||
ATA_REG_LBA4 = $0A;
|
||||
ATA_REG_LBA5 = $0B;
|
||||
ATA_REG_CONTROL = $0C;
|
||||
ATA_REG_ALTSTATUS = $0C;
|
||||
ATA_REG_DEVADDRESS = $0D;
|
||||
|
||||
ATA_DEVICE_MASTER = $A0;
|
||||
ATA_DEVICE_SLAVE = $B0;
|
||||
|
||||
ATA_PRIMARY_BASE = $1F0;
|
||||
|
||||
var
|
||||
controller : PPCI_Device;
|
||||
|
||||
bar0 : uint32;
|
||||
bar1 : uint32;
|
||||
bar4 : uint32;
|
||||
|
||||
IDEDevices : array[0..3] of TIDE_Device;
|
||||
|
||||
buffer : Puint32;
|
||||
|
||||
procedure init();
|
||||
function load(ptr : void) : boolean;
|
||||
function identify_device(bus : uint8; device : uint8) : TIdentResponse;
|
||||
|
||||
// procedure flush();
|
||||
procedure readPIO28(drive : uint8; LBA : uint32; buffer : puint8);
|
||||
procedure writePIO28(drive : uint8; LBA : uint32; buffer : puint8);
|
||||
//read/write must be capable of reading/writting any amknt of data upto disk size
|
||||
|
||||
procedure dread(device : PStorage_device; LBA : uint32; sectorCount : uint32; buffer : puint32);
|
||||
procedure dwrite(device : PStorage_device; LBA : uint32; sectorCount : uint32; buffer : puint32);
|
||||
|
||||
implementation
|
||||
|
||||
function port_read(register : uint8) : uint8;
|
||||
begin
|
||||
port_read:= inb(ATA_PRIMARY_BASE + register);
|
||||
end;
|
||||
|
||||
procedure port_write(register : uint8; data : uint8);
|
||||
var
|
||||
i : uint8;
|
||||
begin
|
||||
outb(ATA_PRIMARY_BASE + register, data);
|
||||
util.psleep(1);
|
||||
if register = ATA_REG_COMMAND then begin
|
||||
for i:= 0 to 5 do begin
|
||||
port_read(ATA_REG_STATUS);
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure no_interrupt(device : uint8);
|
||||
begin
|
||||
outb($3F6, inb($3f6) or (1 shl 1));
|
||||
end;
|
||||
|
||||
procedure device_select(device : uint8);
|
||||
begin
|
||||
outb($1F6, device); //TODO clean
|
||||
end;
|
||||
|
||||
function is_ready() : boolean;
|
||||
var
|
||||
status : uint8;
|
||||
i : uint32;
|
||||
begin
|
||||
//wait for drive to be ready
|
||||
while true do begin
|
||||
status := port_read(ATA_REG_COMMAND);
|
||||
|
||||
if(status and ATA_SR_ERR) = ATA_SR_ERR then begin
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) DRIVE ERROR!');
|
||||
console.redrawWindows();
|
||||
is_ready := false;
|
||||
break;
|
||||
end;
|
||||
|
||||
if (status and ATA_SR_BUSY) <> ATA_SR_BUSY then begin
|
||||
is_ready := true;
|
||||
break;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
function validate_28bit_address(addr : uint32) : boolean;
|
||||
begin
|
||||
validate_28bit_address := (addr and $F0000000) = 0;
|
||||
end;
|
||||
|
||||
function identify_device(bus : uint8; device : uint8) : TIdentResponse;
|
||||
var
|
||||
status : uint8;
|
||||
identResponse : TIdentResponse;
|
||||
i : uint8;
|
||||
begin
|
||||
push_trace('IDE.Identify_Device');
|
||||
device_select(device);
|
||||
no_interrupt(device);
|
||||
port_write(ATA_REG_CONTROL, 0);
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) CHECK FLOATING BUS');
|
||||
|
||||
//check if bus is floating
|
||||
status := port_read(ATA_REG_COMMAND);
|
||||
if status = $FF then exit;
|
||||
|
||||
port_write(ATA_REG_SECCOUNT, 0);
|
||||
port_write(ATA_REG_LBA0, 0);
|
||||
port_write(ATA_REG_LBA1, 0);
|
||||
port_write(ATA_REG_LBA2, 0);
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) SEND IDENTIFY COMMAND');
|
||||
|
||||
port_write(ATA_REG_COMMAND, ATA_CMD_IDENTIFY);
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) WAIT FOR DRIVE TO BE READY');
|
||||
|
||||
//check if drive is present
|
||||
status := port_read(ATA_REG_COMMAND);
|
||||
if status = $00 then exit;
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) WAIT FOR DRIVE TO BE READY');
|
||||
|
||||
if not is_ready() then exit;
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) READ IDENTIFY RESPONSE');
|
||||
|
||||
for i:=0 to 255 do begin
|
||||
console.writeint(i);
|
||||
identResponse[i] := inw(ATA_PRIMARY_BASE + ATA_REG_DATA);
|
||||
end;
|
||||
|
||||
console.writestringln('[IDE] (IDENTIFY_DEVICE) IDENTIFY RESPONSE RECEIVED');
|
||||
|
||||
identify_device := identResponse;
|
||||
end;
|
||||
|
||||
procedure init();
|
||||
var
|
||||
devID : TDeviceIdentifier;
|
||||
begin
|
||||
push_trace('ide.init');
|
||||
console.writestringln('[IDE] (INIT) BEGIN');
|
||||
devID.bus:= biPCI;
|
||||
devID.id0:= idANY;
|
||||
devID.id1:= $00000001;
|
||||
devID.id2:= $00000001;
|
||||
devID.id3:= idANY;
|
||||
devID.id4:= idANY;
|
||||
devID.ex:= nil;
|
||||
drivermanagement.register_driver('IDE ATA Driver', @devID, @load);
|
||||
console.writestringln('[IDE] (INIT) END');
|
||||
end;
|
||||
|
||||
function load(ptr : void) : boolean;
|
||||
var
|
||||
controller : PPCI_Device;
|
||||
masterDevice : TStorage_Device;
|
||||
slaveDevice : TStorage_Device;
|
||||
buffer : puint8;
|
||||
i : uint8;
|
||||
test : PStorage_device;
|
||||
tbuf : puint8;
|
||||
begin
|
||||
push_trace('ide.load');
|
||||
console.writestringln('[IDE] (LOAD) BEGIN');
|
||||
controller := PPCI_Device(ptr);
|
||||
|
||||
console.writestringln('[IDE] (INIT) CHECK FLOATING BUS');
|
||||
//check if bus is floating and identify device
|
||||
if inb($1F7) <> $FF then begin
|
||||
//outb($3F6, inb($3f6) or (1 shl 1)); // disable interrupts
|
||||
IDEDevices[0].isMaster:= true;
|
||||
IDEDevices[0].info := identify_device(0, ATA_DEVICE_MASTER);
|
||||
e
|
||||
mastrDevice.controller := ControllerIDE;
|
||||
masterDevice.controllerId0:= 0;
|
||||
masterDevice.maxSectorCount:= (IDEDevices[0].info[60] or (IDEDevices[0].info[61] shl 16) ); //LBA28 SATA
|
||||
|
||||
if IDEDevices[0].info[1] = 0 then begin
|
||||
console.writestringln('[IDE] (INIT) ERROR: DEVICE IDENT FAILED!');
|
||||
exit;
|
||||
end;
|
||||
|
||||
// masterDevice.hpc:= uint32(IDEDevices[0].info[3] DIV IDEDevices[0].info[1]); //TODO wtf is hpc
|
||||
|
||||
masterDevice.sectorSize:= 512;
|
||||
if masterDevice.maxSectorCount <> 0 then begin
|
||||
IDEDevices[0].exists:= true;
|
||||
masterDevice.readCallback:= @dread;
|
||||
masterDevice.writeCallback:= @dwrite;
|
||||
// storagemanagement.register_device(@masterDevice);
|
||||
drivemanager.register_device(@masterDevice);
|
||||
end;
|
||||
|
||||
end;
|
||||
|
||||
// buffer:= puint8(kalloc(512));
|
||||
// buffer[0] := 1;
|
||||
// buffer[1] := 2;
|
||||
// buffer[2] := 3;
|
||||
// buffer[3] := 4;
|
||||
// buffer[4] := 5;
|
||||
// buffer[5] := 6;
|
||||
// writePIO28(0, 3, buffer);
|
||||
// writePIO28(0, 3, buffer);
|
||||
// writePIO28(0, 3, buffer);
|
||||
// writePIO28(0, 4, buffer);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// psleep(1000);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// writePIO28(0, 5, buffer);
|
||||
// kfree(puint32(buffer));
|
||||
|
||||
console.writestringln('[IDE] (LOAD) END');
|
||||
|
||||
//read first 16 bytes of disk
|
||||
tbuf:= puint8(kalloc(512));
|
||||
|
||||
//set buffer to 1F1F repeating
|
||||
for i:=0 to 200 do begin
|
||||
tbuf[i] := 31;
|
||||
end;
|
||||
|
||||
//write buffer to disk
|
||||
writePIO28(0, 0, tbuf);
|
||||
|
||||
memset(uint32(tbuf), 0, 512);
|
||||
readPIO28(0, 0, puint8(tbuf));
|
||||
console.writestringln('[IDE] (INIT) READ FIRST 4 BYTES OF DISK');
|
||||
console.writehexln(tbuf[0]);
|
||||
console.writehexln(tbuf[1]);
|
||||
console.writehexln(tbuf[2]);
|
||||
console.writehexln(tbuf[3]);
|
||||
kfree(puint32(tbuf));
|
||||
|
||||
|
||||
|
||||
end;
|
||||
|
||||
procedure readPIO28(drive : uint8; LBA : uint32; buffer : puint8);
|
||||
var
|
||||
status : uint8;
|
||||
i: uint16;
|
||||
device: uint8;
|
||||
data: uint16;
|
||||
begin
|
||||
push_trace('IDE.readPIO28');
|
||||
|
||||
if not validate_28bit_address(LBA) then begin
|
||||
console.writestringln('IDE (writePIO28) ERROR: Invalid LBA!');
|
||||
end;
|
||||
|
||||
// push_trace('IDE.readPIO28.2');
|
||||
|
||||
//Add last 4 bits of LBA to device port
|
||||
if IDEDevices[drive].isMaster then begin
|
||||
device:= ATA_DEVICE_MASTER;
|
||||
device_select($E0 or ((LBA and $0F000000) shr 24)); //LBA primary master
|
||||
end
|
||||
else begin
|
||||
device:= ATA_DEVICE_SLAVE;
|
||||
device_select($F0 or ((LBA and $0F000000) shr 24)); //LBA primary slave
|
||||
end;
|
||||
|
||||
// push_trace('IDE.readPIO28.3');
|
||||
|
||||
no_interrupt(device);
|
||||
port_write(ATA_REG_ERROR, 0);
|
||||
|
||||
//Write sector count and LBA
|
||||
port_write(ATA_REG_SECCOUNT, 1);
|
||||
port_write(ATA_REG_LBA0, (LBA and $000000FF));
|
||||
port_write(ATA_REG_LBA1, (LBA and $0000FF00) shr 8);
|
||||
port_write(ATA_REG_LBA2, (LBA and $00FF0000) shr 16);
|
||||
|
||||
// push_trace('IDE.readPIO28.4');
|
||||
|
||||
//send read command
|
||||
port_write(ATA_REG_COMMAND, ATA_CMD_READ_PIO);
|
||||
if not is_ready() then exit;
|
||||
|
||||
i:=0;
|
||||
while i < 512 do begin
|
||||
// if not is_ready() then exit;
|
||||
|
||||
data:= inw(ATA_PRIMARY_BASE + ATA_REG_DATA);
|
||||
|
||||
buffer[i+1] := uint8($00ff and (data shr 8));
|
||||
buffer[i] := uint8($00ff and data);
|
||||
|
||||
i:= i + 2;
|
||||
|
||||
if not is_ready() then exit;
|
||||
end;
|
||||
|
||||
// push_trace('IDE.readPIO28.5');
|
||||
end;
|
||||
|
||||
procedure writePIO28(drive : uint8; LBA : uint32; buffer : puint8);
|
||||
var
|
||||
status : uint8;
|
||||
i: uint16;
|
||||
device: uint8;
|
||||
begin
|
||||
push_trace('IDE.WritePIO28');
|
||||
if not validate_28bit_address(LBA) then begin
|
||||
console.writestringln('IDE (writePIO28) ERROR: Invalid LBA!');
|
||||
end;
|
||||
|
||||
console.writeintln(uint32(drive));
|
||||
console.writeintln(LBA);
|
||||
|
||||
//Add last 4 bits of LBA to device port
|
||||
if IDEDevices[drive].isMaster then begin
|
||||
device:= ATA_DEVICE_MASTER;
|
||||
device_select($E0 or ((LBA and $0F000000) shr 24)); //LBA primary master
|
||||
end
|
||||
else begin
|
||||
device:= ATA_DEVICE_SLAVE;
|
||||
device_select($F0 or ((LBA and $0F000000) shr 24)); //LBA primary slave
|
||||
end;
|
||||
|
||||
// no_interrupt(device);
|
||||
|
||||
port_write(ATA_REG_ERROR, 0);
|
||||
port_write(ATA_REG_CONTROL, 0);
|
||||
|
||||
// check if bus is floating
|
||||
status := port_read(ATA_REG_COMMAND);
|
||||
if status = $FF then exit;
|
||||
|
||||
//Write sector count and LBA
|
||||
port_write(ATA_REG_SECCOUNT, 1);
|
||||
port_write(ATA_REG_LBA0, (LBA and $000000FF));
|
||||
port_write(ATA_REG_LBA1, (LBA and $0000FF00) shr 8);
|
||||
port_write(ATA_REG_LBA2, (LBA and $00FF0000) shr 16);
|
||||
|
||||
//send write command
|
||||
port_write(ATA_REG_COMMAND, ATA_CMD_WRITE_PIO);
|
||||
|
||||
//write data
|
||||
i:=0;
|
||||
while i < 512 do begin
|
||||
outw(ATA_PRIMARY_BASE + ATA_REG_DATA, uint16(buffer[i] or (buffer[i+1] shl 8)));
|
||||
i:= i + 2;
|
||||
end;
|
||||
|
||||
//flush drive cache
|
||||
psleep(1);
|
||||
port_write(ATA_REG_COMMAND, ATA_CMD_CACHE_FLUSH);
|
||||
psleep(1);
|
||||
if not is_ready() then exit;
|
||||
end;
|
||||
|
||||
procedure dread(device : PStorage_device; LBA : uint32; sectorCount : uint32; buffer : Puint32);
|
||||
var
|
||||
i : uint16;
|
||||
begin
|
||||
push_trace('IDE.dread');
|
||||
for i:=0 to sectorCount-1 do begin
|
||||
readPIO28(device^.controllerId0, LBA + i, puint8(@buffer[512*i]));
|
||||
psleep(100)
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure dwrite(device : PStorage_device; LBA : uint32; sectorCount : uint32; buffer : Puint32);
|
||||
var
|
||||
i : uint16;
|
||||
begin
|
||||
for i:=0 to sectorCount-1 do begin
|
||||
writePIO28(device^.controllerId0, LBA + i, puint8(@buffer[512*i]));
|
||||
psleep(100)
|
||||
end;
|
||||
// writePIO28(device^.controllerId0, LBA, puint8(buffer));
|
||||
end;
|
||||
|
||||
end.
|
||||
Loading…
x
Reference in New Issue
Block a user