Spexeah/Asuro
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git-svn-id: https://spexeah.com:8443/svn/Asuro@285 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c

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This commit is contained in:
aaron 2017-10-28 14:11:49 +00:00
parent c00a18e974
commit c6a6169a3b
2 changed files with 104 additions and 3 deletions
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103
src/driver/AHCI.pas
View File

@ -83,8 +83,30 @@ type
data : ^uint32;
end;
// TFIS_PIO_Setup = bitpacked record
// end;
TFIS_PIO_Setup = bitpacked record
fis_type : uint8;
pmport : UBit4;
rsv0 : ubit1;
d : ubit1;
i : ubit1;
rsv1 : ubit1;
status : uint8;
error : uint8;
lba0 : uint8;
lba1 : uint8;
lba2 : uint8;
device : uint8;
lba3 : uint8;
lba4 : uint8;
lba5 : uint8;
rsv2 : uint8;
countl : uint8;
counth : uint8;
rsv3 : uint8;
e_status : uint8;
tc : uint16;
rsv4 : uint16;
end;
// TFIS_DMA_Setup = bitpacked record
// end;
@ -98,8 +120,82 @@ type
// THBA_FIS = bitpacked record
// end;
THBA_PORT = bitpacked record
clb : uint32;
clbu : uint32;
fb : uint32;
fbu : uint32;
istat : uint32;
ie : uint32;
cmd : uint32;
rsv0 : uint32;
tfd : uint32;
sig : uint32;
ssts : uint32;
sctl : uint32;
serr : uint32;
sact : uint32;
ci : uint32;
sntf : uint32;
fbs : uint32;
rsv1[11] : uint32;
vendor[4] : uint32;
end;
THBA_MEM = bitpacked record
cap : uint32; //0
global_host_control : uint32; //4
interrupt_status : uint32; //8
port_implemented : uint32; //c
version : uint32; //10
ccc_control : uint32; //14
ccc_ports : uint32; //18
em_location : uint32; //1c
em_Control : uint32; //20
hcap2 : uint32; //24
bohc : uint32; //28
rsv0 : array[0..210] of ubit1;
ports : array[0..31] of HBA_PORT;
end;
THBAptr : ^THBA_MEM;
TCommand_Header = bitpacked record
cfl : ubit5;
a : ubit1;
w : ubit1;
p : ubit1;
r : ubit1;
b : ubit1;
c : ubit1;
rsv0 : ubit1;
pmp : ubit4;
PRDTL : uint16;
PRDTBC : uint32;
CTBA : uint32;
CTBAU : uint32;
rsv1 : array[0..3] of uint32;
end;
TPRD bitpacked record
data_base_address : uint32;
data_bade_address_U : uint32;
rsv0 : uint32;
data_byte_count : ubit22;
rsv1 : ubit9;
interrupt_oc : ubit1;
end;
var
//constants
SATA_SIG_ATA := $101;
SATA_SIG_ATAPI := $EB140101;
SATA_SIG_SEMB := $C33C0101;
STAT_SIG_PM := $96690101;
//other
PCI_Devices : TDeviceArray;
hba : THBAptr;
procedure init();
@ -109,7 +205,8 @@ procedure init();
var
count : uint16;
begin
//PCI_Devices := PCI.getDeviceInfo(1, 6, @count);
console.writestringln('AHCI: STARTING INIT');
PCI_Devices := PCI.getDeviceInfo(1, 6, 0, count);
end;
end.

4
src/system.pas
View File

@ -61,7 +61,11 @@ type
UBit5 = 0..(1 shl 5) - 1;
UBit6 = 0..(1 shl 6) - 1;
UBit7 = 0..(1 shl 7) - 1;
UBit9 = 0..(1 shl 9) - 1;
UBit17 = 0..(1 shl 17) - 1;
UBit20 = 0..(1 shl 20) - 1;
UBit22 = 0..(1 shl 22) - 1;
UBit25 = 0..(1 shl 25) - 1;
UBit28 = 0..(1 shl 28) - 1;
UBit30 = 0..(1 shl 30) - 1;