From cffe840208669f46bfb3d1ec2fe36b6300911fcb Mon Sep 17 00:00:00 2001 From: aaron Date: Tue, 24 Oct 2017 10:54:15 +0000 Subject: [PATCH] git-svn-id: https://spexeah.com:8443/svn/Asuro@240 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c --- src/driver/ATA.pas | 136 +++++++++++++++++++++++++++++++++++++ src/driver/PCI.pas | 40 ++--------- src/driver/drivertypes.pas | 51 ++++++++++++++ 3 files changed, 192 insertions(+), 35 deletions(-) create mode 100644 src/driver/ATA.pas create mode 100644 src/driver/drivertypes.pas diff --git a/src/driver/ATA.pas b/src/driver/ATA.pas new file mode 100644 index 00000000..6841d8a7 --- /dev/null +++ b/src/driver/ATA.pas @@ -0,0 +1,136 @@ +{ ************************************************ + * Asuro + * Unit: Drivers/ATA + * Description: ATA Driver + ************************************************ + * Author: Aaron Hance + * Contributors: + ************************************************ } +unit ATA; + +{$MACRO ON} +{$define ATA_SR_BSY := 0x80 } +{$define ATA_SR_DRDY := 0x40 } +{$define ATA_SR_DF := 0x20 } +{$define ATA_SR_DSC := 0x10 } +{$define ATA_SR_DRQ := 0x08 } +{$define ATA_SR_CORR := 0x04 } +{$define ATA_SR_IDX := 0x02 } +{$define ATA_SR_ERR := 0x01 } + +{$define ATA_CMD_READ_PIO := 0x20 } +{$define ATA_CMD_READ_PIO_EXT := 0x24 } +{$define ATA_CMD_READ_DMA := 0xC8 } +{$define ATA_CMD_READ_DMA_EXT := 0x25 } +{$define ATA_CMD_WRITE_PIO := 0x30 } +{$define ATA_CMD_WRITE_PIO_EXT := 0x34 } +{$define ATA_CMD_WRITE_DMA := 0xCA } +{$define ATA_CMD_WRITE_DMA_EXT := 0x35 } +{$define ATA_CMD_CACHE_FLUSH := 0xE7 } +{$define ATA_CMD_CACHE_FLUSH_EXT := 0xEA } +{$define ATA_CMD_PACKET := 0xA0 } +{$define ATA_CMD_IDENTIFY_PACKET := 0xA1 } +{$define ATA_CMD_IDENTIFY := 0xEC } + +{$define ATAPI_CMD_READ := 0xA8 } +{$define ATAPI_CMD_EJECT := 0x1B } + +{$define ATA_IDENT_DEVICETYPE := 0 } +{$define ATA_IDENT_CYLINDERS := 2 } +{$define ATA_IDENT_HEADS := 6 } +{$define ATA_IDENT_SECTORS := 12 } +{$define ATA_IDENT_SERIAL := 20 } +{$define ATA_IDENT_MODEL := 54 } +{$define ATA_IDENT_CAPABILITIES := 98 } +{$define ATA_IDENT_FIELDVALID := 106 } +{$define ATA_IDENT_MAX_LBA := 120 } +{$define ATA_IDENT_COMMANDSETS := 164 } +{$define ATA_IDENT_MAX_LBA_EXT := 200 } + +{$define IDE_ATA := 0x00 } +{$define IDE_ATAPI := 0x01 } + +{$define ATA_MASTER := 0x00 } +{$define ATA_SLAVE := 0x01 } + +{$define ATA_REG_DATA := 0x00 } +{$define ATA_REG_ERROR := 0x01 } +{$define ATA_REG_FEATURES := 0x01 } +{$define ATA_REG_SECCOUNT0 := 0x02 } +{$define ATA_REG_LBA0 := 0x03 } +{$define ATA_REG_LBA1 := 0x04 } +{$define ATA_REG_LBA2 := 0x05 } +{$define ATA_REG_HDDEVSEL := 0x06 } +{$define ATA_REG_COMMAND := 0x07 } +{$define ATA_REG_STATUS := 0x07 } +{$define ATA_REG_SECCOUNT1 := 0x08 } +{$define ATA_REG_LBA3 := 0x09 } +{$define ATA_REG_LBA4 := 0x0A } +{$define ATA_REG_LBA5 := 0x0B } +{$define ATA_REG_CONTROL := 0x0C } +{$define ATA_REG_ALTSTATUS := 0x0C } +{$define ATA_REG_DEVADDRESS := 0x0D } + +interface + +uses + util, + drivertypes, + console, + terminal; + +type + + IDE_Channel_Registers = record + base : uint16; + ctrl : uint16; + bmide : uint16; + nIEN : uint8; + end; + + IDE_Device = record + Reserved : uint8; + Channel : uint8; + Drive : uint8; + dType : uint16; + Signature : uint16; + Capabilities : uint16; + CommandSets : uint32; + Size : uint32; + Model : array[0..41] of uint8; + end; + +var + ATA1 : uint32; + ATA2 : uint32; + ATA3 : uint32; + ATA4 : uint32; + BUS_MASTER : uint32; + + channels : array[0..1] of IDE_Channel_Registers; + devices : array[0..3] of IDE_Device; + + ide_buff : array[0..2048] of uint8; + ide_irq_invoked : uint8 = 0; + atapi_packet : array[0..11] of uint8 = ($AB, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + + + +procedure init(device : TPCI_Device); + +implementation + +procedure init(device : TPCI_Device); + begin + ATA1 := device.address0; + ATA2 := device.address1; + ATA3 := device.address2; + ATA4 := device.address3; + BUS_MASTER := device.address4; + + console.writehexln(ATA1); + console.writehexln(ATA2); + console.writehexln(BUS_MASTER); +end; + +end. \ No newline at end of file diff --git a/src/driver/PCI.pas b/src/driver/PCI.pas index 7c9cb1b5..5428a94f 100644 --- a/src/driver/PCI.pas +++ b/src/driver/PCI.pas @@ -13,7 +13,9 @@ interface uses util, - console; + console, + drivertypes, + ATA; type @@ -110,40 +112,7 @@ type address : ubit30; //4-byte aligned reserved : boolean; always_0 : boolean; - end; - - TPCI_Device = packed record - device_id : uint16; - vendor_id : uint16; - status : uint16; - command : uint16; - class_code : uint8; - subclass_class : uint8; - prog_if : uint8; - revision_id : uint8; - BIST : uint8; - header_type : uint8; - latency_timer : uint8; - cache_size : uint8; - address0 : uint32; - address1 : uint32; - address2 : uint32; - address3 : uint32; - address4 : uint32; - address5 : uint32; - CIS_pointer : uint32; - subsystem_id : uint16; - subsystem_vid : uint16; - exp_rom_addr : uint32; - reserved0 : uint16; - reserved1 : uint8; - capabilities : uint8; - reserved2 : uint32; - max_latency : uint8; - min_grant : uint8; - interrupt_pin : uint8; - interrupt_line : uint8; - end; + end; TPCI_Device_Bridge = bitpacked record device_id : uint16; @@ -433,6 +402,7 @@ begin if tmp.class_code = 1 then begin console.writestringln('-Device is MASS_STORAGE_CONTROLLER '); + if tmp.subclass_class = 1 then ATA.init(tmp); end; if tmp.class_code = 2 then begin console.writestringln('-Device is NETWORK_CONTROLLER '); diff --git a/src/driver/drivertypes.pas b/src/driver/drivertypes.pas new file mode 100644 index 00000000..49e339bd --- /dev/null +++ b/src/driver/drivertypes.pas @@ -0,0 +1,51 @@ +{ ************************************************ + * Asuro + * Unit: Drivers/drivertypes + * Description: types shared between drivers + ************************************************ + * Author: Aaron Hance + * Contributors: + ************************************************ } +unit drivertypes; + +interface + +type + + TPCI_Device = packed record + device_id : uint16; + vendor_id : uint16; + status : uint16; + command : uint16; + class_code : uint8; + subclass_class : uint8; + prog_if : uint8; + revision_id : uint8; + BIST : uint8; + header_type : uint8; + latency_timer : uint8; + cache_size : uint8; + address0 : uint32; + address1 : uint32; + address2 : uint32; + address3 : uint32; + address4 : uint32; + address5 : uint32; + CIS_pointer : uint32; + subsystem_id : uint16; + subsystem_vid : uint16; + exp_rom_addr : uint32; + reserved0 : uint16; + reserved1 : uint8; + capabilities : uint8; + reserved2 : uint32; + max_latency : uint8; + min_grant : uint8; + interrupt_pin : uint8; + interrupt_line : uint8; + end; + +implementation + + +end.