Spexeah/Asuro
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git-svn-id: https://spexeah.com:8443/svn/Asuro@295 6dbc8c32-bb84-406f-8558-d1cf31a0ab0c

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This commit is contained in:
aaron 2018-04-05 08:41:53 +00:00
parent d3b5e21acf
commit d90838c052
1 changed files with 49 additions and 29 deletions
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72
src/driver/AHCI.pas
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@ -15,7 +15,8 @@ uses
util, util,
PCI, PCI,
drivertypes, drivertypes,
drivermanagement; drivermanagement,
lmemorymanager;
type type
@ -87,10 +88,10 @@ type
TFIS_PIO_Setup = bitpacked record TFIS_PIO_Setup = bitpacked record
fis_type : uint8; fis_type : uint8;
pmport : UBit4; pmport : UBit4;
rsv0 : ubit1; rsv0 : boolean;
d : ubit1; d : boolean;
i : ubit1; i : boolean;
rsv1 : ubit1; rsv1 : boolean;
status : uint8; status : uint8;
error : uint8; error : uint8;
lba0 : uint8; lba0 : uint8;
@ -139,8 +140,8 @@ type
ci : uint32; ci : uint32;
sntf : uint32; sntf : uint32;
fbs : uint32; fbs : uint32;
rsv1[11] : uint32; rsv1 : array[0..11] of uint32;
vendor[4] : uint32; vendor : array[0..4] of uint32;
end; end;
THBA_MEM = bitpacked record THBA_MEM = bitpacked record
@ -155,8 +156,8 @@ type
em_Control : uint32; //20 em_Control : uint32; //20
hcap2 : uint32; //24 hcap2 : uint32; //24
bohc : uint32; //28 bohc : uint32; //28
rsv0 : array[0..210] of ubit1; rsv0 : array[0..210] of boolean;
ports : array[0..31] of HBA_PORT; ports : array[0..31] of THBA_Port;
end; end;
THBAptr : ^THBA_MEM; THBAptr : ^THBA_MEM;
@ -164,13 +165,13 @@ type
TCommand_Header = bitpacked record TCommand_Header = bitpacked record
cfl : ubit5; cfl : ubit5;
a : ubit1; a : boolean;
w : ubit1; w : boolean;
p : ubit1; p : boolean;
r : ubit1; r : boolean;
b : ubit1; b : boolean;
c : ubit1; c : boolean;
rsv0 : ubit1; rsv0 : boolean;
pmp : ubit4; pmp : ubit4;
PRDTL : uint16; PRDTL : uint16;
PRDTBC : uint32; PRDTBC : uint32;
@ -179,32 +180,35 @@ type
rsv1 : array[0..3] of uint32; rsv1 : array[0..3] of uint32;
end; end;
TCommand_Table bitpacked record TCommand_Table = bitpacked record
cfis : array[0..64] of uint8; cfis : array[0..64] of uint8;
acmd : array[0..16] of uint8; acmd : array[0..16] of uint8;
rsv : array[0..48] of uint8; rsv : array[0..48] of uint8;
prdt : array[0..1] of TPRD_Entry; prdt : array[0..1] of TPRD_Entry;
end; end;
TPRD_Entry bitpacked record TPRD_Entry = bitpacked record
data_base_address : uint32; data_base_address : uint32;
data_bade_address_U : uint32; data_bade_address_U : uint32;
rsv0 : uint32; rsv0 : uint32;
data_byte_count : ubit22; data_byte_count : ubit22;
rsv1 : ubit9; rsv1 : ubit9;
interrupt_oc : ubit1; interrupt_oc : boolean;
end; end;
var var
//constants //constants
SATA_SIG_ATA := $101; //SATA_SIG_ATA := $101;
SATA_SIG_ATAPI := $EB140101; //SATA_SIG_ATAPI := $EB140101;
SATA_SIG_SEMB := $C33C0101; //STA_SIG_SEMB := $C33C0101;
STAT_SIG_PM := $96690101; //STAT_SIG_PM := $96690101;
//other //other
ahciController : intptr; ahciController : intptr;
hba : THBAptr; hba : THBAptr;
sataStorageDevices : array[0..31] of intptr;
sataStorageDeviceCount : uint8;
procedure init(); procedure init();
@ -226,16 +230,32 @@ function register_device(ptr : void) : boolean
begin begin
ahciController := ptr; ahciController := ptr;
hba := ahciController.address5; hba := ahciController.address5;
check_ports();
exit(true); exit(true);
end; end;
procedure check_ports(); procedure check_ports();
var var
d : uint32;
i : uint32; i : uint32;
ii : uint32;
begin begin
i:= 1; d:= 1;
while true do begin activePorts : array[0..32] of uint32;
// if i and hba^.port_implemented != 1 for i:= 0 to 31 do begin
if d and hba^.port_implemented != 0 then // port connected
begin
if hba^.ports[i].ssts == 259 then // port in use and active
begin
if hba^.ports[i].sig == 1 then //device is sata
begin
sataStorageDevices[sataStorageDeviceCount - 1] := @hba^.ports[i];
sataStorageDeviceCount += 1;
end
//TODO implement other types
end
end
d := d shl 1;
end end
end end