657 lines
20 KiB
ObjectPascal
657 lines
20 KiB
ObjectPascal
unit E1000;
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interface
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uses
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tracer,
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console,
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strings,
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vmemorymanager,
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lmemorymanager,
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drivermanagement,
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drivertypes,
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util,
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IDT,
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PCI,
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terminal,
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net,
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nettypes,
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netutils,
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isrmanager;
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const
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INTEL_VEND = $8086;
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E1000_DEV = $100E;
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I217_DEV = $153A;
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LM82577_DEV = $10EA;
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REG_CTRL = $0000;
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REG_STATUS = $0008;
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REG_EEPROM = $0014;
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REG_CTRL_EXT = $0018;
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REG_IMASK = $00D0;
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REG_RCTRL = $0100;
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REG_RXDESCLO = $2800;
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REG_RXDESCHI = $2804;
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REG_RXDESCLEN = $2808;
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REG_RXDESCHEAD = $2810;
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REG_RXDESCTAIL = $2818;
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REG_TCTRL = $0400;
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REG_TXDESCLO = $3800;
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REG_TXDESCHI = $3804;
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REG_TXDESCLEN = $3808;
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REG_TXDESCHEAD = $3810;
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REG_TXDESCTAIL = $3818;
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REG_RDTR = $2820; // RX Delay Timer Register
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REG_RXDCTL = $3828; // RX Descriptor Control
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REG_RADV = $282C; // RX Int. Absolute Delay Timer
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REG_RSRPD = $2C00; // RX Small Packet Detect Interrupt
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REG_TIPG = $0410; // Transmit Inter Packet Gap
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ECTRL_SLU = $40; //set link up
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RCTL_EN = (1 SHL 1); // Receiver Enable
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RCTL_SBP = (1 SHL 2); // Store Bad Packets
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RCTL_UPE = (1 SHL 3); // Unicast Promiscuous Enabled
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RCTL_MPE = (1 SHL 4); // Multicast Promiscuous Enabled
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RCTL_LPE = (1 SHL 5); // Long Packet Reception Enable
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RCTL_LBM_NONE = (0 SHL 6); // No Loopback
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RCTL_LBM_PHY = (3 SHL 6); // PHY or external SerDesc loopback
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RTCL_RDMTS_HALF = (0 SHL 8); // Free Buffer Threshold is 1/2 of RDLEN
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RTCL_RDMTS_QUARTER = (1 SHL 8); // Free Buffer Threshold is 1/4 of RDLEN
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RTCL_RDMTS_EIGHTH = (2 SHL 8); // Free Buffer Threshold is 1/8 of RDLEN
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RCTL_MO_36 = (0 SHL 12); // Multicast Offset - bits 47:36
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RCTL_MO_35 = (1 SHL 12); // Multicast Offset - bits 46:35
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RCTL_MO_34 = (2 SHL 12); // Multicast Offset - bits 45:34
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RCTL_MO_32 = (3 SHL 12); // Multicast Offset - bits 43:32
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RCTL_BAM = (1 SHL 15); // Broadcast Accept Mode
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RCTL_VFE = (1 SHL 18); // VLAN Filter Enable
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RCTL_CFIEN = (1 SHL 19); // Canonical Form Indicator Enable
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RCTL_CFI = (1 SHL 20); // Canonical Form Indicator Bit Value
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RCTL_DPF = (1 SHL 22); // Discard Pause Frames
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RCTL_PMCF = (1 SHL 23); // Pass MAC Control Frames
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RCTL_SECRC = (1 SHL 26); // Strip Ethernet CRC
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// Buffer Sizes
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RCTL_BSIZE_256 = (3 SHL 16);
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RCTL_BSIZE_512 = (2 SHL 16);
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RCTL_BSIZE_1024 = (1 SHL 16);
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RCTL_BSIZE_2048 = (0 SHL 16);
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RCTL_BSIZE_4096 = ((3 SHL 16) OR (1 SHL 25));
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RCTL_BSIZE_8192 = ((2 SHL 16) OR (1 SHL 25));
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RCTL_BSIZE_16384 = ((1 SHL 16) OR (1 SHL 25));
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// Transmit Command
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CMD_EOP = (1 SHL 0); // End of Packet
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CMD_IFCS = (1 SHL 1); // Insert FCS
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CMD_IC = (1 SHL 2); // Insert Checksum
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CMD_RS = (1 SHL 3); // Report Status
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CMD_RPS = (1 SHL 4); // Report Packet Sent
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CMD_VLE = (1 SHL 6); // VLAN Packet Enable
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CMD_IDE = (1 SHL 7); // Interrupt Delay Enable
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// TCTL Register
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TCTL_EN = (1 SHL 1); // Transmit Enable
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TCTL_PSP = (1 SHL 3); // Pad Short Packets
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TCTL_CT_SHIFT = 4; // Collision Threshold
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TCTL_COLD_SHIFT = 12; // Collision Distance
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TCTL_SWXOFF = (1 SHL 22); // Software XOFF Transmission
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TCTL_RTLC = (1 SHL 24); // Re-transmit on Late Collision
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TSTA_DD = (1 SHL 0); // Descriptor Done
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TSTA_EC = (1 SHL 1); // Excess Collisions
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TSTA_LC = (1 SHL 2); // Late Collision
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LSTA_TU = (1 SHL 3); // Transmit Underrun
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E1000_NUM_RX_DESC = 32;
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E1000_NUM_TX_DESC = 8;
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type
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PE1000_rx_desc = ^TE1000_rx_desc;
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TE1000_rx_desc = bitpacked record
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address : uint64;
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length : uint16;
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checksum : uint16;
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status : uint8;
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errors : uint8;
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special : uint16;
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end;
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PE1000_tx_desc = ^TE1000_tx_desc;
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TE1000_tx_desc = bitpacked record
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address : uint64;
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length : uint16;
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cso : uint8;
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cmd : uint8;
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status : uint8;
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css : uint8;
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special : uint16;
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end;
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TCardType = (ctUnknown, ctE1000, ctI217, ct82577LM);
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procedure init();
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function getMACAddress : puint8;
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function sendPacket(p_data : void; p_len : uint16) : sint32;
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function readStatus : uint32;
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implementation
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var
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bus, slot, func : uint8;
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loaded : boolean;
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card_type : TCardType;
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bar_type : uint8;
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io_base : uint16;
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mem_base : uint64;
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eeprom_exists : boolean;
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mac : array[0..5] of uint8;
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rx_descs : array[0..E1000_NUM_RX_DESC-1] of PE1000_rx_desc;
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tx_descs : array[0..E1000_NUM_TX_DESC-1] of PE1000_tx_desc;
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rx_buffs : array[0..E1000_NUM_RX_DESC-1] of puint8;
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rx_curr : uint16;
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tx_curr : uint16;
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mem_aloc : boolean = false;
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procedure writeCommand(p_address : uint16; p_value : uint32);
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var
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mem : puint32;
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begin
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push_trace('E1000.writeCommand');
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if (bar_type = 0) then begin
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mem:= puint32(mem_base + p_address);
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mem^:= p_value;
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end else begin
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outl(io_base + 0, p_address);
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outl(io_base + 4, p_address)
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end;
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pop_trace;
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end;
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function readCommand(p_address : uint16) : uint32;
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var
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mem : puint32;
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begin
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push_trace('E1000.readCommand');
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if (bar_type = 0) then begin
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mem:= puint32(mem_base + p_address);
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readCommand:= mem^;
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end else begin
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outl(io_base, p_address);
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readCommand:= inl(io_base + 4);
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end;
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pop_trace;
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end;
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function readStatus : uint32;
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begin
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readStatus:= readCommand(REG_STATUS);
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end;
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function detectEEPROM() : boolean;
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var
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val, i : uint32;
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begin
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push_trace('E1000.detectEEPROM');
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val:= 0;
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writeCommand(REG_EEPROM, $1);
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for i:=0 to 1000 do begin
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if eeprom_exists then break;
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val:= readCommand(REG_EEPROM);
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if (val and $10) > 0 then eeprom_exists:= true else eeprom_exists:= false;
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end;
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detectEEPROM:= eeprom_exists;
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pop_trace;
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end;
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function EEPROMRead( address : uint8 ) : uint32;
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var
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data : uint16;
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tmp : uint32;
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begin
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push_trace('E1000.EEPROMRead');
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tmp:= 0;
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if (eeprom_exists) then begin
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writeCommand( REG_EEPROM, 1 OR (uint32(address) SHL 8) );
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while (tmp AND (1 SHL 4)) = 0 do begin
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tmp:= readCommand(REG_EEPROM); //Might be wrong?
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end;
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end else begin
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writeCommand( REG_EEPROM, 1 OR (uint32(address) SHL 2) );
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while (tmp AND (1 SHL 1)) = 0 do begin
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tmp:= readCommand(REG_EEPROM); //Might be wrong?
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end;
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end;
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data:= uint16( (tmp SHR 16) AND ($FFFF) );
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EEPROMRead:= data;
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pop_trace;
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end;
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function readMACAddress() : boolean;
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var
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temp : uint32;
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mem_base_mac_8 : puint8;
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mem_base_mac_32 : puint32;
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res : boolean;
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i : uint32;
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begin
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push_trace('E1000.readMACAddress');
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res:= true;
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if (eeprom_exists) then begin
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temp:= EEPROMRead(0);
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mac[0]:= temp AND $FF;
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mac[1]:= temp SHR 8;
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temp:= EEPROMRead(1);
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mac[2]:= temp AND $FF;
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mac[3]:= temp SHR 8;
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temp:= EEPROMRead(2);
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mac[4]:= temp AND $FF;
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mac[5]:= temp SHR 8;
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end else begin
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mem_base_mac_8:= puint8(mem_base + $5400);
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mem_base_mac_32:= puint32(mem_base + $5400);
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if (mem_base_mac_32[0] <> 0) then begin
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for i:=0 to 6 do begin
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mac[i]:= mem_base_mac_8[i];
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end;
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end else begin
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res:= false;
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end;
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end;
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readMACAddress:= res;
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pop_trace;
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end;
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procedure startLink();
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var
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val : uint32;
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begin
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push_trace('E1000.startLink');
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val:= readCommand(REG_CTRL);
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writeCommand(REG_CTRL, val OR ECTRL_SLU);
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pop_trace;
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end;
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procedure rxinit();
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var
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ptr : puint8;
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outptr : puint8;
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descs : PE1000_rx_desc;
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i : uint32;
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begin
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push_trace('E1000.rxinit');
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ptr:= puint8(kalloc(sizeof(TE1000_rx_desc) * E1000_NUM_RX_DESC + 16));
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descs:= PE1000_rx_desc(ptr);
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for i:=0 to E1000_NUM_RX_DESC do begin
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rx_descs[i]:= @descs[i];//PE1000_rx_desc(uint32(descs) + i*16);
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rx_buffs[i]:= puint8(kalloc(8192 + 16));
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rx_descs[i]^.address:= uint64(vtop(uint32(rx_buffs[i])));
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rx_descs[i]^.status:= 0;
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end;
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outptr:= puint8(vtop(uint32(ptr)));//puint8(uint32(ptr) - KERNEL_VIRTUAL_BASE);
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console.output('E1000 Driver', 'RX VMem: ');
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console.writehexln(uint32(ptr));
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console.output('E1000 Driver', 'RX Mem: ');
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console.writehexln(uint32(outptr));
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writeCommand(REG_TXDESCLO, uint32(uint64(outptr) SHR 32));
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writeCommand(REG_TXDESCHI, uint32(uint64(outptr) AND $FFFFFFFF));
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writeCommand(REG_RXDESCLO, uint32(outptr));
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writeCommand(REG_RXDESCHI, 0);
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writeCommand(REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(TE1000_rx_desc));
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writeCommand(REG_RXDESCHEAD, 0);
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writeCommand(REG_RXDESCTAIL, E1000_NUM_RX_DESC-1);
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rx_curr:= 0;
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writeCommand(REG_RCTRL, RCTL_EN OR RCTL_SBP OR RCTL_UPE OR RCTL_MPE OR RCTL_LBM_NONE OR RTCL_RDMTS_HALF OR RCTL_BAM OR RCTL_SECRC OR RCTL_BSIZE_2048);
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pop_trace;
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end;
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procedure txinit();
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var
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ptr : puint8;
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outptr : puint8;
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descs : PE1000_tx_desc;
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i : uint32;
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begin
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push_trace('E1000.txinit');
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ptr:= puint8(kalloc(sizeof(TE1000_tx_desc) * (E1000_NUM_TX_DESC + 16)));
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descs:= PE1000_tx_desc(ptr);
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for i:=0 to E1000_NUM_TX_DESC do begin
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tx_descs[i]:= @descs[i];//PE1000_tx_desc(uint32(descs + i*16));
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tx_descs[i]^.address:= 0;
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tx_descs[i]^.cmd:= 0;
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tx_descs[i]^.status:= TSTA_DD;
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end;
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outptr:= puint8(vtop(uint32(ptr))); //puint8(uint32(ptr) - KERNEL_VIRTUAL_BASE);
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console.output('E1000 Driver', 'TX VMem: ');
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console.writehexln(uint32(ptr));
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console.output('E1000 Driver', 'TX Mem: ');
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console.writehexln(uint32(outptr));
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writeCommand(REG_TXDESCHI, 0);
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writeCommand(REG_TXDESCLO, uint32(outptr));
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writeCommand(REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(TE1000_tx_desc));
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writeCommand( REG_TXDESCHEAD, 0 );
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writeCommand( REG_TXDESCTAIL, 0 );
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tx_curr:= 0;
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writeCommand(REG_TCTRL, TCTL_EN OR TCTL_PSP OR (15 SHL TCTL_CT_SHIFT) OR (64 SHL TCTL_COLD_SHIFT) OR TCTL_RTLC);
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//The following is needed for I217 & 82577LM
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if (card_type = ct82577LM) OR (card_type = ctI217) then begin
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writeCommand(REG_TCTRL, $3003F0FA);
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writeCommand(REG_TIPG, $0060200A);
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end;
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pop_trace;
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end;
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procedure enableInturrupt();
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begin
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push_trace('E1000.enableInterrupt');
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writeCommand(REG_IMASK, $1F6DC);
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writeCommand(REG_IMASK, $FF AND NOT(4));
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readCommand($C0);
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pop_trace;
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end;
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procedure handleReceive();
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var
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old_cur : uint16;
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got_packet : boolean;
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buf : puint8;
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len : uint16;
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i : uint16;
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begin
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push_trace('E1000.handleReceive');
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while (rx_descs[rx_curr]^.status AND $1) > 0 do begin
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got_packet:= true;
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buf:= rx_buffs[rx_curr];
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len:= rx_descs[rx_curr]^.length;
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//Inject Packet into Network Stack
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net.recv(void(buf), len);
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rx_descs[rx_curr]^.status:= 0;
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old_cur:= rx_curr;
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rx_curr:= (rx_curr + 1) mod E1000_NUM_RX_DESC;
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writeCommand(REG_RXDESCTAIL, old_cur);
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end;
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pop_trace;
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end;
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procedure writeCardType();
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begin
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console.output('E1000 Driver', 'Card Type: ');
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case card_type of
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ctUnknown:writestringln('Unknown');
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ct82577LM:writestringln('82577LM');
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ctE1000:writestringln('Generic E1000');
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ctI217:writestringln('I217');
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end;
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end;
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procedure fire();
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var
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status : uint32;
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data : uint32;
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begin
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push_trace('E1000.fire');
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writeToLogLn('L0: E1000 Fire');
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status:= readCommand($C0);
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if (status AND $04) > 0 then begin
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startLink();
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end else if (Status AND $10) > 0 then begin
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//Good Threshold
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end else if (Status AND $80) > 0 then begin
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handleReceive();
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end;
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//Clear the INT on the Device First by using write-1
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writeCommand(REG_IMASK, 1);
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end;
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procedure console_command_mac(params : PParamList);
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begin
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push_trace('E1000.console_command_mac');
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writeMACAddress(@mac[0], getTerminalHWND);
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pop_trace;
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end;
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procedure console_command_sendtest(params : PParamList);
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var
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TestPacket : Array[0..41] of uint8 = ( $ff, $ff, $ff, $ff, $ff, $ff, { eth dest (broadcast) }
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$52, $54, $00, $12, $34, $56, { eth source }
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$08, $06, { eth type }
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$00, $01, { ARP htype }
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$08, $00, { ARP ptype }
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$06, { ARP hlen }
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$04, { ARP plen }
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$00, $01, { ARP opcode: ARP_REQUEST }
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$52, $54, $00, $12, $34, $56, { ARP hsrc }
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169, 254, 13, 37, { ARP psrc }
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$00, $00, $00, $00, $00, $00, { ARP hdst }
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192, 168, 0, 128 { ARP pdst }
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);
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begin
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push_trace('E1000.console_command_sendtest');
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TestPacket[6]:= mac[0];
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TestPacket[7]:= mac[1];
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TestPacket[8]:= mac[2];
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TestPacket[9]:= mac[3];
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TestPacket[10]:= mac[4];
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TestPacket[11]:= mac[5];
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TestPacket[22]:= mac[0];
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TestPacket[23]:= mac[1];
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TestPacket[24]:= mac[2];
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TestPacket[25]:= mac[3];
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TestPacket[26]:= mac[4];
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TestPacket[27]:= mac[5];
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sendPacket(void(@TestPacket[0]), 42);
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writeStringlnWND('E1000 ARP Testpacket Sent.', getTerminalHWND);
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pop_trace;
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end;
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procedure terminal_command_e1000status(Params : PParamList);
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begin
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console.writestringWND('Card: ', getTerminalHWND);
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case card_type of
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ctUnknown:console.writestringlnWND('Unknown', getTerminalHWND);
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ctE1000:console.writestringlnWND('E1000 Generic', getTerminalHWND);
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ct82577LM:console.writestringlnWND('82577LM', getTerminalHWND);
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ctI217:console.writestringlnWND('I217', getTerminalHWND);
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else console.writestringlnWND('UNIDENTIFIED!!!', getTerminalHWND);
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end;
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console.writestringWND('Status: ', getTerminalHWND);
|
|
console.writeHexLnWND(readStatus, getTerminalHWND);
|
|
|
|
console.writestringWND('CTRL: ', getTerminalHWND);
|
|
console.writehexlnWND(readCommand(REG_CTRL), getTerminalHWND);
|
|
|
|
console.writestringWND('TX Curr: ', getTerminalHWND);
|
|
console.writeintWND(tx_curr, getTerminalHWND);
|
|
console.writestringWND('/', getTerminalHWND);
|
|
console.writeintlnWND(E1000_NUM_TX_DESC, getTerminalHWND);
|
|
|
|
console.writestringWND('RX Curr: ', getTerminalHWND);
|
|
console.writeintWND(rx_curr, getTerminalHWND);
|
|
console.writestringWND('/', getTerminalHWND);
|
|
console.writeintlnWND(E1000_NUM_RX_DESC, getTerminalHWND);
|
|
|
|
console.writestringWND('RX MEM: ', getTerminalHWND);
|
|
console.writeHexLnWND(uint32(@rx_descs[0]), getTerminalHWND);
|
|
|
|
console.writestringWND('TX MEM: ', getTerminalHWND);
|
|
console.writeHexLnWND(uint32(@tx_descs[0]), getTerminalHWND);
|
|
end;
|
|
|
|
function load(ptr : void) : boolean;
|
|
var
|
|
PCI_Info : PPCI_Device;
|
|
i : uint32;
|
|
data : uint32;
|
|
iline : uint8;
|
|
|
|
begin
|
|
push_trace('E1000.load');
|
|
|
|
console.outputln('E1000 Driver', 'Load Start.');
|
|
|
|
writeCardType();
|
|
|
|
PCI_Info:= PPCI_Device(ptr);
|
|
bar_type:= PCI_Info^.address0 AND $00000001;
|
|
io_base:= PCI_Info^.address0 AND $FFFFFFF0;
|
|
mem_base:= PCI_INFO^.address0 AND $FFFFFFFC;
|
|
|
|
{ !!!!! Dirty way to alloc the pages, needs fixing !!!!! }
|
|
kpalloc(io_base);
|
|
kpalloc(mem_base);
|
|
|
|
bus:= PCI_Info^.bus;
|
|
slot:= PCI_Info^.slot;
|
|
func:= PCI_Info^.func;
|
|
setBusMaster(PCI_Info^.bus, PCI_Info^.slot, PCI_Info^.func, true);
|
|
eeprom_exists:= false;
|
|
|
|
detectEEPROM();
|
|
if eeprom_exists then console.outputln('E1000 Driver', 'EEPROM Exists: YES.') else console.outputln('E1000 Driver', 'EEPROM Exists: NO.');
|
|
if not readMACAddress() then begin
|
|
console.outputln('E1000 Driver', 'MAC Read Failed.');
|
|
load:= false;
|
|
end else begin
|
|
console.output('E1000 Driver', 'MAC Address: ');
|
|
writeMACAddress(@mac[0], 0);
|
|
|
|
startLink();
|
|
|
|
for i:=0 to $80 do begin
|
|
writeCommand($5200 + i*4, 0);
|
|
end;
|
|
|
|
net.registerNetworkCard(@sendPacket, getMACAddress());
|
|
|
|
isrmanager.registerISR(32 + PCI_Info^.interrupt_line, @fire);
|
|
//IDT.set_gate(32 + PCI_Info^.interrupt_line, uint32(@fire), $08, ISR_RING_0);
|
|
enableInturrupt();
|
|
|
|
rxinit();
|
|
txinit();
|
|
|
|
load:= true;
|
|
|
|
if load then registercommand('E1000', @terminal_command_e1000status, 'E1000 Information.');
|
|
if load then registercommand('MAC', @console_command_mac, 'Print MAC Address.');
|
|
end;
|
|
|
|
console.outputln('E1000 Driver', 'Load Finish.');
|
|
|
|
pop_trace;
|
|
end;
|
|
|
|
function loadE1000(ptr : void) : boolean;
|
|
begin
|
|
push_trace('E1000.loadE1000');
|
|
loadE1000:= false;
|
|
if not Loaded then begin
|
|
card_type:= ctE1000;
|
|
loadE1000:= load(ptr);
|
|
end;
|
|
pop_trace;
|
|
end;
|
|
|
|
function load82577LM(ptr : void) : boolean;
|
|
begin
|
|
push_trace('E1000.load82577LM');
|
|
load82577LM:= false;
|
|
if not Loaded then begin
|
|
card_type:= ct82577LM;
|
|
load82577LM:= load(ptr);
|
|
end;
|
|
pop_trace;
|
|
end;
|
|
|
|
function loadI217(ptr : void) : boolean;
|
|
begin
|
|
push_trace('E1000.loadI217');
|
|
loadI217:= false;
|
|
if not Loaded then begin
|
|
card_type:= ctI217;
|
|
loadI217:= load(ptr);
|
|
end;
|
|
pop_trace;
|
|
end;
|
|
|
|
procedure init();
|
|
var
|
|
dev : TDeviceIdentifier;
|
|
|
|
begin
|
|
push_trace('E1000.init');
|
|
card_type:= ctUnknown;
|
|
dev.Bus:= biPCI;
|
|
dev.id0:= INTEL_VEND;
|
|
dev.id1:= idANY;
|
|
dev.id2:= idANY;
|
|
dev.id3:= idANY;
|
|
dev.id4:= E1000_DEV;
|
|
dev.ex:= nil;
|
|
drivermanagement.register_driver('E1000 Ethernet Driver', @dev, @loadE1000);
|
|
dev.id4:= I217_DEV;
|
|
drivermanagement.register_driver('I217 Ethernet Driver', @dev, @loadI217);
|
|
dev.id4:= LM82577_DEV;
|
|
drivermanagement.register_driver('82577LM Ethernet Driver', @dev, @load82577LM);
|
|
pop_trace;
|
|
end;
|
|
|
|
function getMACAddress : puint8;
|
|
begin
|
|
getMACAddress:= puint8(@mac[0]);
|
|
end;
|
|
|
|
function sendPacket(p_data : void; p_len : uint16) : sint32;
|
|
var
|
|
old_cur : uint8;
|
|
timeout : uint32;
|
|
|
|
begin
|
|
push_trace('E1000.sendPacket');
|
|
tx_descs[tx_curr]^.address:= uint32(vtop(uint32(p_data)));
|
|
tx_descs[tx_curr]^.length:= p_len;
|
|
tx_descs[tx_curr]^.cmd:= CMD_EOP OR CMD_IFCS OR CMD_RS OR CMD_RPS;
|
|
tx_descs[tx_curr]^.status:= 0;
|
|
old_cur:= tx_curr;
|
|
tx_curr:= (tx_curr + 1) MOD E1000_NUM_TX_DESC;
|
|
writeCommand(REG_TXDESCTAIL, tx_curr);
|
|
timeout:= 1000000;
|
|
while ((tx_descs[old_cur]^.status AND $FF) = 0) and (timeout > 0) do begin
|
|
dec(timeout);
|
|
end;
|
|
sendPacket:= 1;
|
|
if timeout > 0 then sendPacket:= 0;
|
|
pop_trace;
|
|
end;
|
|
|
|
end. |