Spexeah/Asuro

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t3hn3rd 2d190c221a feature: boot.mgr replace hardcoded init sequence with dependency-driven boot manager

Introduce boot.mgr - a self-registering, dependency-ordered boot
initialization framework with barrier-based phasing and glob pattern
matching. Units now declare their own init procedures and dependencies
via registerBoot()/registerBarrier() in their initialization sections,
boot.mgr.run() topologically sorts and executes them.

- Add src/boot/boot.mgr.pas with topoSort, glob matching, barrier
  two-pass algorithm, and boot tree printer
- Gut src/asuro.pas (kmain): now just stores multiboot info, calls
  System.init(), boot.mgr.run, and yield()
- Add initialization sections with registerBoot() to 53 existing units
- Add new units: core.pas, test.pas, driver.storage.boot.pas,
  app.wasm.pas, app.bsod.pas (factored out of asuro.pas)
- Define 9 barrier phases: immediate -> early -> middle -> storage ->
  bus -> device -> bus.late -> late -> final
- Fix xHCI ISR: exclude PRC/WRC from PORTSC change bit clearing to
  prevent race with port reset busy-wait
- Fix driver.bus.usb.core fire_completion_hooks: guard against uint32
  underflow when CompletionHookCount = 0
- Move auto_mount_volumes from device barrier to late barrier so it
  runs after PCI scan discovers storage controllers
- Add toolchain/compile_initcalls.sh for boot entry extraction
- Add Boot Registration sections to all 51 doc files; create 4 new
  doc files; rewrite boot.mgr.md; update mkdocs.yml nav

2026-03-13 15:37:43 +00:00

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arch.x86.irq

PIC (8259A) initialisation and IRQ remapping.

Overview

This unit reinitialises and remaps the two 8259A Programmable Interrupt Controllers. By default, the BIOS leaves the master PIC with IRQs 0–7 mapped to CPU interrupt vectors 0x08–0x0F, which conflicts with x86 exception vectors. This unit sends the standard initialisation command sequence to both PICs and remaps IRQs 0–7 to vectors 0x20–0x27 (master) and IRQs 8–15 to vectors 0x28–0x2F (slave), placing all hardware IRQs safely above the reserved exception range.

Dependencies

core.util
arch.x86.util
io.syslog

Boot Registration

Registered with boot.mgr as arch.x86.irq, depending on arch.x86.idt.

Functions and Procedures

init

procedure init();

Reinitialises both 8259A PICs using the ICW (Initialisation Command Word) sequence:

Sends ICW1 ($11) to both master (port $20) and slave (port $A0) command ports — edge-triggered, cascade mode, ICW4 required.
Sends ICW2: master base vector $20 (IRQ 0 maps to INT 32), slave base vector $28 (IRQ 8 maps to INT 40).
Sends ICW3: master cascade on IRQ line 2 ($04), slave cascade identity ($02).
Sends ICW4 ($01) to both PICs — 8086/88 mode.
Clears both interrupt masks ($00) so all IRQ lines are unmasked.

An io_wait call is inserted between each port write to give the PIC hardware time to process each command byte.

Notes

After init, IRQ 0 (PIT timer) is at vector 0x20, IRQ 1 (PS/2 keyboard) at 0x21, and so on through IRQ 15 at vector 0x2F.
On systems with an I/O APIC, the 8259 PICs operate in Virtual Wire mode, and additional configuration is performed by arch.x86.isr.ioapic.
This unit does not install any ISR handlers; handler registration is the responsibility of arch.x86.isr.mgr and the individual ISR units.

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