Spexeah/Asuro

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t3hn3rd 2d190c221a feature: boot.mgr replace hardcoded init sequence with dependency-driven boot manager

Introduce boot.mgr - a self-registering, dependency-ordered boot
initialization framework with barrier-based phasing and glob pattern
matching. Units now declare their own init procedures and dependencies
via registerBoot()/registerBarrier() in their initialization sections,
boot.mgr.run() topologically sorts and executes them.

- Add src/boot/boot.mgr.pas with topoSort, glob matching, barrier
  two-pass algorithm, and boot tree printer
- Gut src/asuro.pas (kmain): now just stores multiboot info, calls
  System.init(), boot.mgr.run, and yield()
- Add initialization sections with registerBoot() to 53 existing units
- Add new units: core.pas, test.pas, driver.storage.boot.pas,
  app.wasm.pas, app.bsod.pas (factored out of asuro.pas)
- Define 9 barrier phases: immediate -> early -> middle -> storage ->
  bus -> device -> bus.late -> late -> final
- Fix xHCI ISR: exclude PRC/WRC from PORTSC change bit clearing to
  prevent race with port reset busy-wait
- Fix driver.bus.usb.core fire_completion_hooks: guard against uint32
  underflow when CompletionHookCount = 0
- Move auto_mount_volumes from device barrier to late barrier so it
  runs after PCI scan discovers storage controllers
- Add toolchain/compile_initcalls.sh for boot entry extraction
- Add Boot Registration sections to all 51 doc files; create 4 new
  doc files; rewrite boot.mgr.md; update mkdocs.yml nav

2026-03-13 15:37:43 +00:00

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arch.x86.isr.mgr

Interrupt Service Routine registration, dispatch, and IDT gate management.

Overview

This unit is the central ISR management layer. It maintains a two-dimensional hook table indexed by interrupt vector number and hook slot, installs naked assembly stubs (ISR_0 through ISR_255) in the IDT for all 256 vectors, and dispatches registered callbacks when interrupts fire. It also handles End-of-Interrupt (EOI) signalling to both the 8259 PIC and, when present, the Local APIC.

Each ISR stub is declared with the Free Pascal interrupt directive, which causes the compiler to generate PUSHAD/POPAD prologue and epilogue code and use IRETD to return. The stub saves EBP into the global IntReg pointer before calling the common dispatch function ISR_N.

Dependencies

arch.x86.isr
arch.x86.idt
arch.x86.isr.types
core.util
arch.x86.util
io.syslog (implementation)
arch.x86.isr.ioapic (implementation)

Boot Registration

Registered with boot.mgr as arch.x86.isr.mgr, depending on arch.x86.irq.

Constants

MAX_HOOKS is imported from arch.x86.isr.types and defines the maximum number of callbacks per vector.

Types

TISRHook

TISRHook = procedure();

Type of a no-argument, no-return ISR callback procedure.

TISRNHookArray

TISRNHookArray = Array[0..MAX_HOOKS] of TISRHook;

Array of hook callbacks for a single interrupt vector.

TISRHookArray

TISRHookArray = Array[0..255] of TISRNHookArray;

Two-dimensional array of all hook callbacks, indexed by vector number then hook slot.

Functions and Procedures

init

procedure init;

Installs assembly ISR stubs for all 256 vectors into the IDT using arch.x86.idt.set_gate with selector $08 and ISR_RING_0 flags. All hook slots are initialised to nil during unit startup.

registerISR

procedure registerISR(INT_N : uint8; callback : TISRHook);

Registers a callback for interrupt vector INT_N. Scans the hook slot array for the first empty slot (nil entry) and assigns callback to it. Up to MAX_HOOKS callbacks may be registered per vector.

INT_N — The IDT vector number (0–255).
callback — The procedure to invoke when the interrupt fires.

dispatchHooks

procedure dispatchHooks(INT_N : uint8);

Iterates through all MAX_HOOKS slots for vector INT_N and calls each non-nil callback. Does not send EOI. Used by the context switch ISR (arch.x86.proc.sched) to fire timer hooks before sending EOI independently.

Notes

The internal ISR_N procedure dispatches all hooks for a given vector, sends a Local APIC EOI via arch.x86.isr.ioapic.lapic_eoi, and then sends an 8259 EOI. For slave PIC interrupts (vectors 40–47), the slave EOI ($A0) is sent before the master EOI ($20).
The context switch ISR (arch.x86.proc.sched.context_switch_isr) replaces IDT gate 32 after init is called and manages its own EOI, bypassing ISR_N for the timer vector.
The interrupt procedure directive on each ISR stub causes Free Pascal to generate the correct PUSHAD/POPAD frame and IRETD. The EBP register at the start of this frame is saved to IntReg so that fault handlers can locate the saved register state.

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