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ATA, (PATAPI dead), AHCI New Begginings

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This commit is contained in:
Aaron
2025-03-14 19:49:56 +00:00
parent fd0de9f1d2
commit 0855abfd41
6 changed files with 475 additions and 40 deletions
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src/driver/storage/AHCI/AHCI.pas
+56
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@@ -0,0 +1,56 @@
unit AHCI;
interface
uses
util,
PCI,
drivertypes,
drivermanagement,
lmemorymanager,
console,
vmemorymanager,
AHCITypes;
var
ahciControllers : array[0..255] of pointer;
ahciControllerCount : uint32;
hba : array[0..255] of THBA_Memory;
procedure init();
procedure load();
implementation
procedure init();
var
devID : TDeviceIdentifier;
begin
console.writestringln('AHCI: Registering driver');
devID.bus:= biPCI;
devID.id0:= idANY;
devID.id1:= $00000001;
devID.id2:= $00000006;
devID.id3:= $00000001;
devID.id4:= idANY;
devID.ex:= nil;
drivermanagement.register_driver('ATA/PI AHCI Driver', @devID, @load);
end;
procedure load(ptr : void);
begin
// console.writestringln('AHCI: initilizing a new controller');
// ahciControllers[ahciControllerCount] := ptr;
// hba[ahciControllerCount] := PPCI_Device(ptr)^.address5;
// new_page_at_address(hba[ahciControllerCount]);
// //here would be any controller setup needed
// check_ports(ahciControllerCount);
// ahciControllerCount += 1;
// exit(true);
end;
end.
src/driver/storage/AHCI/AHCITypes.pas
+172
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File diff suppressed because it is too large Load Diff
src/driver/storage/IDE.pas
+65 -10
View File
@@ -17,28 +17,29 @@ uses
tracer,
drivemanager,
storagetypes,
idetypes;
idetypes,
isrmanager;
var
primaryDevices: array[0..1] of TIDE_Device = (
(exists: false; isPrimary: true; isMaster: true; isATAPI: false;
status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
base: ATA_PRIMARY_BASE; info: nil),
base: ATA_PRIMARY_BASE; blockSize: 0; info: nil),
(exists: false; isPrimary: true; isMaster: false; isATAPI: false;
status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
base: ATA_PRIMARY_BASE; info: nil)
base: ATA_PRIMARY_BASE; blockSize: 0; info: nil)
);
secondaryDevices: array[0..1] of TIDE_Device = (
(exists: false; isPrimary: false; isMaster: true; isATAPI: false;
status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
base: ATA_SECONDARY_BASE; info: nil),
base: ATA_SECONDARY_BASE; blockSize: 0; info: nil),
(exists: false; isPrimary: false; isMaster: false; isATAPI: false;
status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
base: ATA_SECONDARY_BASE; info: nil)
base: ATA_SECONDARY_BASE; blockSize: 0; info: nil)
);
@@ -47,6 +48,8 @@ var
function get_status(var device : TIDE_Device) : TIDE_Status;
function wait_for_device(device : TIDE_Device; ioop : boolean) : boolean;
procedure no_interrupt(isPrimary : boolean);
procedure enable_interrupt(isPrimary : boolean);
procedure reset_device(device : TIDE_Device);
procedure select_device(device : TIDE_Device);
implementation
@@ -64,6 +67,51 @@ begin
end;
end;
procedure enable_interrupt(isPrimary : boolean);
var
reg : uint8;
begin
if isPrimary then begin
reg := inb(ATA_INTERRUPT_PRIMARY);
reg := reg and not (1 shl 1);
outb(ATA_INTERRUPT_PRIMARY, reg);
end else begin
reg := inb(ATA_INTERRUPT_SECONDARY);
reg := reg and not (1 shl 1);
outb(ATA_INTERRUPT_SECONDARY, reg);
end;
end;
//soft reset
procedure reset_device(device : TIDE_Device);
var
reg : uint8;
begin
if device.isPrimary then begin
reg := inb(ATA_INTERRUPT_PRIMARY);
reg := reg and (1 shl 2);
outb(ATA_INTERRUPT_PRIMARY, reg);
end else begin
reg := inb(ATA_INTERRUPT_SECONDARY);
reg := reg and (1 shl 2);
outb(ATA_INTERRUPT_SECONDARY, reg);
end;
sleep(20);
if device.isPrimary then begin
reg := inb(ATA_INTERRUPT_PRIMARY);
reg := reg and not (1 shl 2);
outb(ATA_INTERRUPT_PRIMARY, reg);
end else begin
reg := inb(ATA_INTERRUPT_SECONDARY);
reg := reg and not (1 shl 2);
outb(ATA_INTERRUPT_SECONDARY, reg);
end;
end;
{
Wait for the device to be ready on the IDE bus
@@ -105,6 +153,7 @@ end;
procedure select_device(device : TIDE_Device);
var
dev : uint8;
reg : uint8;
begin
push_trace('ide.select_device()');
@@ -114,7 +163,10 @@ begin
dev := ATA_DEVICE_MASTER;
end;
outb(device.base + ATA_REG_HDDEVSEL, dev);
reg := inb(device.base + ATA_REG_HDDEVSEL);
reg := (reg and $F0) or dev;
outb(device.base + ATA_REG_HDDEVSEL, reg);
pop_trace();
end;
@@ -201,6 +253,7 @@ Write 0x00 back to Control Register to complete reset.
sleep(1);
// outb(ATA_PRIMARY_BASE1, $00);
// outb(ATA_SECONDARY_BASE1, $00);
select_device(device);
sleep(1);
@@ -246,10 +299,8 @@ var
success : boolean;
size : uint32;
begin
push_trace('ide.load_device()');
success := check_device_type(device);
select_device(device);
if (is_device_present(device) and success) then begin
console.writestringln('[IDE] (load_device) Device is present');
@@ -297,7 +348,7 @@ begin
storageDevice^.writable := false; //TODO atapi
size := atapi.get_device_size(device);
storageDevice^.maxSectorCount := size;
storageDevice^.sectorSize := 2048; //todo
storageDevice^.sectorSize := device.blockSize;
if (device.isMaster) then begin
storageDevice^.controllerId0 := 0;
@@ -390,7 +441,11 @@ var
begin
push_trace('ide.load()');
console.writestringln('[IDE] (load) Loading IDE Devices');
console.redrawWindows();
registerISR(14, @atapi.ide_irq);
registerISR(15, @atapi.ide_irq);
console.writestringln('[IDE] (load) Loading IDE Devices 2');
console.redrawWindows();
pciDevice := PPCI_Device(ptr);
load_device(primaryDevices[0]);
src/driver/storage/atapi.pas
+172 -30
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File diff suppressed because it is too large Load Diff
src/driver/storage/idetypes.pas
+1
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@@ -131,6 +131,7 @@ type
isATAPI : boolean;
status : TIDE_Status;
base : uint16;
blockSize : uint32;
info : PIdentResponse;
end;
src/isr/isrmanager.pas
+9
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@@ -33,6 +33,8 @@ procedure init;
procedure registerISR(INT_N : uint8; callback : TISRHook);
implementation
uses
console;
var
Hooks : TISRHookArray;
@@ -56,6 +58,13 @@ var
i : uint8;
begin
// if int_n <> $20 then begin
// console.writestring('ISR: ');
// console.writehexpair(Int_N);
// console.writestringln(' called');
// end;
for i:=0 to MAX_HOOKS do begin
if Hooks[INT_N][i] <> nil then Hooks[INT_N][i]();
end;