ATA, (PATAPI dead), AHCI New Begginings
This commit is contained in:
@@ -0,0 +1,56 @@
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unit AHCI;
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interface
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uses
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util,
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PCI,
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drivertypes,
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drivermanagement,
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lmemorymanager,
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console,
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vmemorymanager,
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AHCITypes;
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var
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ahciControllers : array[0..255] of pointer;
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ahciControllerCount : uint32;
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hba : array[0..255] of THBA_Memory;
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procedure init();
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procedure load();
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implementation
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procedure init();
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var
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devID : TDeviceIdentifier;
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begin
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console.writestringln('AHCI: Registering driver');
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devID.bus:= biPCI;
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devID.id0:= idANY;
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devID.id1:= $00000001;
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devID.id2:= $00000006;
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devID.id3:= $00000001;
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devID.id4:= idANY;
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devID.ex:= nil;
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drivermanagement.register_driver('ATA/PI AHCI Driver', @devID, @load);
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end;
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procedure load(ptr : void);
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begin
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// console.writestringln('AHCI: initilizing a new controller');
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// ahciControllers[ahciControllerCount] := ptr;
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// hba[ahciControllerCount] := PPCI_Device(ptr)^.address5;
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// new_page_at_address(hba[ahciControllerCount]);
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// //here would be any controller setup needed
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// check_ports(ahciControllerCount);
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// ahciControllerCount += 1;
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// exit(true);
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end;
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end.
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File diff suppressed because it is too large
Load Diff
+65
-10
@@ -17,28 +17,29 @@ uses
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tracer,
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tracer,
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drivemanager,
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drivemanager,
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storagetypes,
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storagetypes,
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idetypes;
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idetypes,
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isrmanager;
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var
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var
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primaryDevices: array[0..1] of TIDE_Device = (
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primaryDevices: array[0..1] of TIDE_Device = (
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(exists: false; isPrimary: true; isMaster: true; isATAPI: false;
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(exists: false; isPrimary: true; isMaster: true; isATAPI: false;
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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base: ATA_PRIMARY_BASE; info: nil),
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base: ATA_PRIMARY_BASE; blockSize: 0; info: nil),
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(exists: false; isPrimary: true; isMaster: false; isATAPI: false;
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(exists: false; isPrimary: true; isMaster: false; isATAPI: false;
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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base: ATA_PRIMARY_BASE; info: nil)
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base: ATA_PRIMARY_BASE; blockSize: 0; info: nil)
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);
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);
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secondaryDevices: array[0..1] of TIDE_Device = (
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secondaryDevices: array[0..1] of TIDE_Device = (
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(exists: false; isPrimary: false; isMaster: true; isATAPI: false;
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(exists: false; isPrimary: false; isMaster: true; isATAPI: false;
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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base: ATA_SECONDARY_BASE; info: nil),
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base: ATA_SECONDARY_BASE; blockSize: 0; info: nil),
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(exists: false; isPrimary: false; isMaster: false; isATAPI: false;
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(exists: false; isPrimary: false; isMaster: false; isATAPI: false;
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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status: (Busy: false; Ready: false; Fault: false; Seek: false; DRQ: false; CORR: false; IDDEX: false; ERROR: false);
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base: ATA_SECONDARY_BASE; info: nil)
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base: ATA_SECONDARY_BASE; blockSize: 0; info: nil)
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);
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);
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@@ -47,6 +48,8 @@ var
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function get_status(var device : TIDE_Device) : TIDE_Status;
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function get_status(var device : TIDE_Device) : TIDE_Status;
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function wait_for_device(device : TIDE_Device; ioop : boolean) : boolean;
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function wait_for_device(device : TIDE_Device; ioop : boolean) : boolean;
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procedure no_interrupt(isPrimary : boolean);
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procedure no_interrupt(isPrimary : boolean);
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procedure enable_interrupt(isPrimary : boolean);
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procedure reset_device(device : TIDE_Device);
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procedure select_device(device : TIDE_Device);
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procedure select_device(device : TIDE_Device);
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implementation
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implementation
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@@ -64,6 +67,51 @@ begin
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end;
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end;
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end;
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end;
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procedure enable_interrupt(isPrimary : boolean);
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var
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reg : uint8;
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begin
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if isPrimary then begin
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reg := inb(ATA_INTERRUPT_PRIMARY);
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reg := reg and not (1 shl 1);
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outb(ATA_INTERRUPT_PRIMARY, reg);
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end else begin
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reg := inb(ATA_INTERRUPT_SECONDARY);
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reg := reg and not (1 shl 1);
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outb(ATA_INTERRUPT_SECONDARY, reg);
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end;
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end;
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//soft reset
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procedure reset_device(device : TIDE_Device);
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var
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reg : uint8;
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begin
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if device.isPrimary then begin
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reg := inb(ATA_INTERRUPT_PRIMARY);
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reg := reg and (1 shl 2);
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outb(ATA_INTERRUPT_PRIMARY, reg);
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end else begin
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reg := inb(ATA_INTERRUPT_SECONDARY);
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reg := reg and (1 shl 2);
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outb(ATA_INTERRUPT_SECONDARY, reg);
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end;
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sleep(20);
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if device.isPrimary then begin
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reg := inb(ATA_INTERRUPT_PRIMARY);
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reg := reg and not (1 shl 2);
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outb(ATA_INTERRUPT_PRIMARY, reg);
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end else begin
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reg := inb(ATA_INTERRUPT_SECONDARY);
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reg := reg and not (1 shl 2);
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outb(ATA_INTERRUPT_SECONDARY, reg);
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end;
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end;
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{
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{
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Wait for the device to be ready on the IDE bus
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Wait for the device to be ready on the IDE bus
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@@ -105,6 +153,7 @@ end;
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procedure select_device(device : TIDE_Device);
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procedure select_device(device : TIDE_Device);
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var
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var
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dev : uint8;
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dev : uint8;
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reg : uint8;
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begin
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begin
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push_trace('ide.select_device()');
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push_trace('ide.select_device()');
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@@ -114,7 +163,10 @@ begin
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dev := ATA_DEVICE_MASTER;
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dev := ATA_DEVICE_MASTER;
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end;
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end;
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outb(device.base + ATA_REG_HDDEVSEL, dev);
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reg := inb(device.base + ATA_REG_HDDEVSEL);
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reg := (reg and $F0) or dev;
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outb(device.base + ATA_REG_HDDEVSEL, reg);
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pop_trace();
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pop_trace();
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end;
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end;
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@@ -201,6 +253,7 @@ Write 0x00 back to Control Register to complete reset.
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sleep(1);
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sleep(1);
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// outb(ATA_PRIMARY_BASE1, $00);
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// outb(ATA_PRIMARY_BASE1, $00);
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// outb(ATA_SECONDARY_BASE1, $00);
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// outb(ATA_SECONDARY_BASE1, $00);
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select_device(device);
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sleep(1);
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sleep(1);
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@@ -246,10 +299,8 @@ var
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success : boolean;
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success : boolean;
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size : uint32;
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size : uint32;
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begin
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begin
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push_trace('ide.load_device()');
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push_trace('ide.load_device()');
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success := check_device_type(device);
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success := check_device_type(device);
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select_device(device);
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if (is_device_present(device) and success) then begin
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if (is_device_present(device) and success) then begin
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console.writestringln('[IDE] (load_device) Device is present');
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console.writestringln('[IDE] (load_device) Device is present');
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@@ -297,7 +348,7 @@ begin
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storageDevice^.writable := false; //TODO atapi
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storageDevice^.writable := false; //TODO atapi
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size := atapi.get_device_size(device);
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size := atapi.get_device_size(device);
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storageDevice^.maxSectorCount := size;
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storageDevice^.maxSectorCount := size;
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storageDevice^.sectorSize := 2048; //todo
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storageDevice^.sectorSize := device.blockSize;
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if (device.isMaster) then begin
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if (device.isMaster) then begin
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storageDevice^.controllerId0 := 0;
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storageDevice^.controllerId0 := 0;
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@@ -390,7 +441,11 @@ var
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begin
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begin
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push_trace('ide.load()');
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push_trace('ide.load()');
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console.writestringln('[IDE] (load) Loading IDE Devices');
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console.writestringln('[IDE] (load) Loading IDE Devices');
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console.redrawWindows();
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registerISR(14, @atapi.ide_irq);
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registerISR(15, @atapi.ide_irq);
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console.writestringln('[IDE] (load) Loading IDE Devices 2');
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console.redrawWindows();
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pciDevice := PPCI_Device(ptr);
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pciDevice := PPCI_Device(ptr);
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load_device(primaryDevices[0]);
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load_device(primaryDevices[0]);
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+167
-25
File diff suppressed because it is too large
Load Diff
@@ -131,6 +131,7 @@ type
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isATAPI : boolean;
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isATAPI : boolean;
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status : TIDE_Status;
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status : TIDE_Status;
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base : uint16;
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base : uint16;
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blockSize : uint32;
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info : PIdentResponse;
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info : PIdentResponse;
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end;
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end;
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@@ -33,6 +33,8 @@ procedure init;
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procedure registerISR(INT_N : uint8; callback : TISRHook);
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procedure registerISR(INT_N : uint8; callback : TISRHook);
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implementation
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implementation
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uses
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console;
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var
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var
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Hooks : TISRHookArray;
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Hooks : TISRHookArray;
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@@ -56,6 +58,13 @@ var
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i : uint8;
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i : uint8;
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begin
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begin
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// if int_n <> $20 then begin
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// console.writestring('ISR: ');
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// console.writehexpair(Int_N);
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// console.writestringln(' called');
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// end;
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for i:=0 to MAX_HOOKS do begin
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for i:=0 to MAX_HOOKS do begin
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if Hooks[INT_N][i] <> nil then Hooks[INT_N][i]();
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if Hooks[INT_N][i] <> nil then Hooks[INT_N][i]();
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end;
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end;
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