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@@ -91,6 +91,7 @@ function getDeviceInfo(class_code : uint8; subclass_code : uint8; prog_if : uint
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procedure requestConfig(bus : uint8; slot : uint8; func : uint8; row : uint8);
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procedure writeConfig(bus: uint8; slot : uint8; func : uint8; row : uint8; val : uint32);
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procedure setBusMaster(bus : uint8; slot : uint8; func : uint8; master : boolean);
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procedure enableDevice(bus : uint8; slot : uint8; func : uint8);
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implementation
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@@ -442,4 +443,32 @@ begin
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pop_trace;
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end;
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//Enable device inturrupts and set bus master
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procedure enableDevice(bus : uint8; slot : uint8; func : uint8);
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var
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addr : uint32;
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cmd : uint32;
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begin
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push_trace('PCI.enableDevice');
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addr := ($1 shl 31);
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addr := addr or (bus shl 16);
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addr := addr or ((slot) shl 11);
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addr := addr or ((func) shl 8);
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addr := addr or ($04 and $FC);
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outl(PCI_CONFIG_ADDRESS_PORT, addr);
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cmd := inl(PCI_CONFIG_DATA_PORT);
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cmd := cmd or PCI_COMMAND_MEM_SPACE;
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cmd := cmd or PCI_COMMAND_BUS_MASTER;
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//enable interrupts, remove disable interrupt bit
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cmd := cmd and not PCI_COMMAND_INT_DISABLE;
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outl(PCI_CONFIG_ADDRESS_PORT, addr);
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outl(PCI_CONFIG_DATA_PORT, cmd);
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pop_trace;
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end;
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end.
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@@ -21,6 +21,23 @@ unit drivertypes;
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interface
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const
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PCI_CONFIG_ADDRESS_PORT = $0CF8;
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PCI_CONFIG_DATA_PORT = $0CFC;
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PCI_COMMAND_IO_SPACE = $0001;
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PCI_COMMAND_MEM_SPACE = $0002;
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PCI_COMMAND_BUS_MASTER = $0004;
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PCI_COMMAND_SPECIAL_CYC = $0008;
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PCI_COMMAND_MEM_WRITE = $0010;
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PCI_COMMAND_VGA_PALETTE = $0020;
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PCI_COMMAND_PARITY = $0040;
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PCI_COMMAND_WAIT = $0080;
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PCI_COMMAND_SERR = $0100;
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PCI_COMMAND_FAST_BACK = $0200;
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PCI_COMMAND_INT_DISABLE = $0400;
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PCI_COMMAND_SERR_ENABLE = $8000;
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type
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PPCI_Device = ^TPCI_Device;
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@@ -44,6 +61,7 @@ type
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address1 : uint32;
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address2 : uint32;
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address3 : uint32;
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address4 : uint32;
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address5 : uint32;
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CIS_pointer : uint32;
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File diff suppressed because it is too large
Load Diff
@@ -72,7 +72,7 @@ type
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rsv0: uint32; // Reserved
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tfd: uint32; // Task File Data
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signature: uint32; // Signature
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sata_stat: uint32; // SATA Status (SCR0:SStatus)
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sata_status: uint32; // SATA Status (SCR0:SStatus)
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sata_ctrl: uint32; // SATA Control (SCR2:SControl)
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sata_error: uint32; // SATA Error (SCR1:SError)
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sata_active: uint32; // SATA Active
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@@ -111,7 +111,7 @@ type
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{
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AHCI Host Bus Adapter (HBA) FIS (Frame Information Structure) Interface
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This structure is used to access the AHCI HBA's FIS (Frame Information Structure)
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memory-mapped registers.
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memory-mapped registers. RX
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}
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THBA_FIS = bitpacked record
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dsfis: array[0..$1F] of uint32; // DMA Setup FIS
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@@ -127,15 +127,53 @@ type
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PHBA_FIS = ^THBA_FIS;
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//enum fis type
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TFISType = (
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FIS_TYPE_REG_H2D = $27, // Register FIS - Host to Device
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FIS_TYPE_REG_D2H = $34, // Register FIS - Device to Host
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FIS_TYPE_DMA_ACT = $39, // DMA Activate FIS - Device to Host
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FIS_TYPE_DMA_SETUP = $41, // DMA Setup FIS - Bidirectional
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FIS_TYPE_DATA = $46, // Data FIS - Bidirectional
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FIS_TYPE_BIST = $58, // BIST Activate FIS - Bidirectional
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FIS_TYPE_PIO_SETUP = $5F, // PIO Setup FIS - Device to Host
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FIS_TYPE_DEV_BITS = $A1 // Set Device Bits FIS - Device to Host
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);
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{
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AHCI Host Bus Adapter (HBA) FIS (Frame Information Structure) Interface
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This structure is used to access the AHCI HBA's FIS (Frame Information Structure)
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}
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THBA_FIS_REG_H2D = bitpacked record
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fis_type: uint8; // FIS Type
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pmport: uint8; // Port Multiplier Port
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command: uint8; // Command
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featurel: uint8; // Feature Lower 8-bits
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lba0: uint8; // LBA0
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lba1: uint8; // LBA1
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lba2: uint8; // LBA2
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device: uint8; // Device
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lba3: uint8; // LBA3
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lba4: uint8; // LBA4
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lba5: uint8; // LBA5
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featureh: uint8; // Feature Upper 8-bits
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countl: uint8; // Count Lower 8-bits
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counth: uint8; // Count Upper 8-bits
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icc: uint8; // Isochronous Command Completion
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control: uint8; // Control
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rsv0: array[0..2] of uint8;
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end;
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PHBA_FIS_REG_H2D = ^THBA_FIS_REG_H2D;
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{
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AHCI Host Bus Adapter (HBA) Command Header Interface
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This structure is used to access the AHCI HBA's Command Header memory-mapped
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registers.
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}
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THBA_CMD_HEADER = bitpacked record
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cmd_fis_length: uint8; // Command FIS Length
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atapi: uint8; // ATAPI
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write: uint8; // Write
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wrt: uint8; // Write
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prefetchable: uint8; // Prefetchable
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reset: uint8; // Reset
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bist: uint8; // BIST
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@@ -152,14 +190,28 @@ type
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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This structure is used to access the AHCI HBA's Command Table memory-mapped
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registers. The AHCI HBA's Command Table memory-mapped registers are used to
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configure the HBA and to issue commands to the SATA devices connected to the HBA.
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}
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THBA_PRD = bitpacked record
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dba: uint32; // Data Base Address
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dbau: uint32; // Data Base Address Upper 32-bits
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rsv0: uint32; // Reserved
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reserved: ubit9; // Reserved
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dbc: ubit22; // Data Byte Count
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int: ubit1; // Interrupt
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// dbc: uint32; // Data Byte Count, bit 1 is Interrupt, then 22 bits of Byte Count, then 9 bits of Reserved
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end;
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TPRDT = array[0..31] of THBA_PRD;
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PPRDT = ^TPRDT;
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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}
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THBA_CMD_TABLE = bitpacked record
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cmd_fis: THBA_FIS; // Command FIS
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acmd: array[0..$1F] of uint8; // ATAPI Command
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rsv0: array[0..$30] of uint8;
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cmd_fis: array[0..63] of uint8; // Command FIS
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acmd: array[0..15] of uint8; // ATAPI Command
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rsv0: array[0..47] of uint8;
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prdt: TPRDT; // Physical Region Descriptor Table
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end;
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PHBA_CMD_TABLE = ^THBA_CMD_TABLE;
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@@ -167,42 +219,6 @@ type
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TCMD_LIST = array[0..255] of THBA_CMD_HEADER;
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PCMD_LIST = ^TCMD_LIST;
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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This structure is used to access the AHCI HBA's Command Table memory-mapped
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registers.
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}
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THBA_PRD = bitpacked record
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dba: uint32; // Data Base Address
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dbau: uint32; // Data Base Address Upper 32-bits
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rsv0: uint32; // Reserved
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dbc: uint32; // Data Byte Count
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rsv1: uint32; // Reserved
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end;
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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This structure is used to access the AHCI HBA's Command Table memory-mapped
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registers.
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}
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THBA_CMD = bitpacked record
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header: THBA_CMD_HEADER; // Command Header
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table: THBA_CMD_TABLE; // Command Table
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prd: array[0..31] of THBA_PRD; // Physical Region Descriptor Table
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end;
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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This structure is used to access the AHCI HBA's Command Table memory-mapped
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registers.
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}
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THBA = bitpacked record
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memory: THBA_Memory; // HBA Memory
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cmd: array[0..$7FF] of THBA_CMD; // Command List
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end;
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PHBA = ^THBA;
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//////////////////////////////////////////
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//////////// Asuro AHCI types ////////////
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//////////////////////////////////////////
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