there you go ki-ear-ron
This commit is contained in:
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@ -91,6 +91,7 @@ function getDeviceInfo(class_code : uint8; subclass_code : uint8; prog_if : uint
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procedure requestConfig(bus : uint8; slot : uint8; func : uint8; row : uint8);
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procedure writeConfig(bus: uint8; slot : uint8; func : uint8; row : uint8; val : uint32);
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procedure setBusMaster(bus : uint8; slot : uint8; func : uint8; master : boolean);
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procedure enableDevice(bus : uint8; slot : uint8; func : uint8);
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implementation
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@ -442,4 +443,32 @@ begin
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pop_trace;
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end;
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//Enable device inturrupts and set bus master
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procedure enableDevice(bus : uint8; slot : uint8; func : uint8);
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var
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addr : uint32;
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cmd : uint32;
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begin
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push_trace('PCI.enableDevice');
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addr := ($1 shl 31);
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addr := addr or (bus shl 16);
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addr := addr or ((slot) shl 11);
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addr := addr or ((func) shl 8);
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addr := addr or ($04 and $FC);
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outl(PCI_CONFIG_ADDRESS_PORT, addr);
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cmd := inl(PCI_CONFIG_DATA_PORT);
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cmd := cmd or PCI_COMMAND_MEM_SPACE;
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cmd := cmd or PCI_COMMAND_BUS_MASTER;
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//enable interrupts, remove disable interrupt bit
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cmd := cmd and not PCI_COMMAND_INT_DISABLE;
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outl(PCI_CONFIG_ADDRESS_PORT, addr);
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outl(PCI_CONFIG_DATA_PORT, cmd);
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pop_trace;
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end;
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end.
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@ -21,6 +21,23 @@ unit drivertypes;
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interface
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const
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PCI_CONFIG_ADDRESS_PORT = $0CF8;
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PCI_CONFIG_DATA_PORT = $0CFC;
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PCI_COMMAND_IO_SPACE = $0001;
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PCI_COMMAND_MEM_SPACE = $0002;
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PCI_COMMAND_BUS_MASTER = $0004;
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PCI_COMMAND_SPECIAL_CYC = $0008;
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PCI_COMMAND_MEM_WRITE = $0010;
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PCI_COMMAND_VGA_PALETTE = $0020;
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PCI_COMMAND_PARITY = $0040;
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PCI_COMMAND_WAIT = $0080;
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PCI_COMMAND_SERR = $0100;
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PCI_COMMAND_FAST_BACK = $0200;
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PCI_COMMAND_INT_DISABLE = $0400;
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PCI_COMMAND_SERR_ENABLE = $8000;
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type
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PPCI_Device = ^TPCI_Device;
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@ -44,6 +61,7 @@ type
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address1 : uint32;
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address2 : uint32;
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address3 : uint32;
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address4 : uint32;
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address5 : uint32;
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CIS_pointer : uint32;
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@ -31,7 +31,9 @@ uses
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console,
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vmemorymanager,
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AHCITypes,
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lists;
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lists,
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idetypes,
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isrmanager;
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var
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ahciControllers : PDList;
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@ -39,6 +41,9 @@ var
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procedure init();
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function load(ptr : void) : boolean;
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procedure check_ports(controller : PAHCI_Controller);
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procedure identify_device(controller : PAHCI_Controller; port : uint32);
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procedure ahci_isr();
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implementation
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@ -60,44 +65,76 @@ end;
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procedure stop_port(port : PHBA_Port);
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begin
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port^.cmd_sts := port^.cmd_sts and not $1; ///maybe also bit 4
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while (port^.cmd_sts and $1) = 1 do begin
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port^.cmd := port^.cmd and not $1; ///maybe also bit 4
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while (port^.cmd and $1) = 1 do begin
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//wait for the port to stop
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end;
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end;
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procedure start_port(port : PHBA_Port);
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begin
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port^.cmd_sts := port^.cmd_sts or $1; ///maybe also bit 4
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while (port^.cmd_sts and $1) = 0 do begin
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port^.cmd := port^.cmd or $1; ///maybe also bit 4
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while (port^.cmd and $1) = 0 do begin
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//wait for the port to start
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end;
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end;
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{
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Check the ports on the controller and setup the command list, FIS, and command table
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}
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procedure check_ports(controller : PAHCI_Controller);
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var
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i : uint32;
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ii : uint32;
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port : PHBA_Port;
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device : PAHCI_Device;
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cmd_list_base : puint32;
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fis_base : puint32;
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cmd_table_base : puint32;
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cmd_header : PHBA_CMD_HEADER;
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command_header : PHBA_CMD_HEADER;
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begin
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console.writestring('AHCI: active ports: ');
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console.writehexln(controller^.mio^.ports_implimented);
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for i:=0 to 31 do begin
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if (controller^.mio^.port_implemented shr i) = 1 then begin
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if (controller^.mio^.ports_implimented shr i) = 1 then begin
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port := @controller^.mio^.ports[i];
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console.writestring('AHCI: Port ');
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console.writeint(i);
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console.writestring(' implemented on controller ');
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console.writehexln(uint32(controller^.pci_device^.address5));
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//check if the port is active TODO
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// if ((port^.sata_status shr 8) <> 1) and ((port^.sata_status and $0F) <> 3) then begin
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// continue; wrong
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// end;
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console.writestring('AHCI: signature: ');
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console.writehexln(port^.signature);
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//check device type
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case port^.signature of
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SATA_SIG_ATA: begin
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console.writestringln('AHCI: Device is SATA');
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device^.device_type := SATA;
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end;
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SATA_SIG_ATAPI: begin
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console.writestringln('AHCI: Device is ATAPI');
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device^.device_type := ATAPI;
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end;
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SATA_SIG_SEMB: begin
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console.writestringln('AHCI: Device is SEMB');
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device^.device_type := SEMB;
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end;
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SATA_SIG_PM: begin
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console.writestringln('AHCI: Device is PM');
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device^.device_type := PM;
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end;
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end;
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//NEEED TO STOP the port before doing anything
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stop_port(port);
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device := PAHCI_Device(DL_Add(controller^.devices));
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device^.port := port;
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@ -111,16 +148,16 @@ begin
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fis_base := puint32((uint32(fis_base) + 255) and $FFFFFF00);
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//set the command list base address
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port^.cmd_list_base := uint32(vtop(cmd_list_base)); //todo set virtual address in device
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port^.cmd_list_base_upper := 0;
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port^.cmdl_basel := vtop(uint32(cmd_list_base)); //todo set virtual address in device
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port^.cmdl_baseu := 0;
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memset(uint32(cmd_list_base), 0, sizeof(THBA_CMD_HEADER));
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device^.command_list := PHBA_CMD_HEADER(cmd_list_base);
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//set the FIS base address
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port^.fis_base := uint32(vtop(fis_base));
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port^.fis_base_upper := 0;
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port^.fis_basel := vtop(uint32(fis_base));
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port^.fis_baseu := 0;
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memset(uint32(fis_base), 0, sizeof(THBA_FIS));
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@ -134,32 +171,96 @@ begin
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device^.command_table := PHBA_CMD_TABLE(cmd_table_base);
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//set the command table base address and setup command table
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for i:=0 to 31 do begin
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for ii:=0 to 31 do begin
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//set command header locations
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command_header := PHBA_CMD_HEADER(uint32(cmd_list_base) + (i * sizeof(THBA_CMD_HEADER)));
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command_header := PHBA_CMD_HEADER(uint32(cmd_list_base) + (ii * sizeof(THBA_CMD_HEADER)));
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command_header^.prdtl := 32;
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//TODO do i need to set prdbc byte count here?
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command_header^.cmd_table_base := uint32(vtop(cmd_table_base) + (i * sizeof(THBA_CMD_TABLE));
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command_header^.cmd_table_base_upper := 0;
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memset(uint32(cmd_table_base) + (i * sizeof(THBA_CMD_TABLE)), 0, sizeof(THBA_CMD_TABLE));
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command_header^.cmd_table_base := vtop(uint32(cmd_table_base)) + (ii * sizeof(THBA_CMD_TABLE));
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command_header^.cmd_table_baseu := 0;
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memset(uint32(cmd_table_base) + (ii * sizeof(THBA_CMD_TABLE)), 0, sizeof(THBA_CMD_TABLE));
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end;
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start_port(port);
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//pass devices count as second param
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identify_device(controller, DL_Size(controller^.devices) - 1);
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end;
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end;
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end;
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procedure identify_device(controller : PAHCI_Controller; port : uint32);
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var
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fis : PHBA_FIS_REG_H2D;
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cmd_header : PHBA_CMD_HEADER;
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cmd_table : PHBA_CMD_TABLE;
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cmd : uint32;
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i : uint32;
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buffer :puint32;
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device : PAHCI_Device;
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begin
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device := PAHCI_Device(DL_Get(controller^.devices, port));
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buffer := kalloc(512);
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memset(uint32(buffer), 0, 512);
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cmd_header := device^.command_list;
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cmd_header^.cmd_fis_length := sizeof(THBA_FIS_REG_H2D) div sizeof(uint32);
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cmd_header^.wrt := 0;
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cmd_header^.prdtl := 1;
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//just use first command table for identify as no other commands are running
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cmd_table := device^.command_table;
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cmd_table^.prdt[0].dba := vtop(uint32(buffer));
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cmd_table^.prdt[0].dbc := 511;
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cmd_table^.prdt[0].int := 1;
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fis := PHBA_FIS_REG_H2D(@device^.command_table^.cmd_fis);
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fis^.fis_type := uint8(FIS_TYPE_REG_H2D);
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fis^.pmport := 0;
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fis^.command := ATA_CMD_IDENTIFY;
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fis^.device := 0;
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fis^.lba0 := 0;
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fis^.lba1 := 0;
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fis^.lba2 := 0;
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fis^.lba3 := 0;
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fis^.lba4 := 0;
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fis^.lba5 := 0;
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fis^.countl := 1;
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fis^.counth := 0;
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fis^.featurel := 0;
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fis^.featureh := 0;
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//send the command
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cmd := device^.port^.cmd;
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cmd := cmd or $1;
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device^.port^.cmd := cmd;
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//wait for the command to complete
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while (cmd and $1) = 1 do begin
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cmd := device^.port^.cmd;
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end;
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//check the status of the command
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if (cmd and $2) = 1 then begin
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console.writestringln('AHCI: Error sending identify command');
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end;
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//parse the identify data
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for i:=0 to 63 do begin
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console.writehex(uint32(buffer[i]));
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console.writestring(' ');
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end;
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console.writestringln('');
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end;
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// procedure identify_device(controller : PAHCI_Controller; port : uint32);
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// var
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// fis : PFIS_REG_H2D;
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// cmd : uint32;
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// i : uint32;
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// begin
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// end;
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function load(ptr : void) : boolean;
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var
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device : PPCI_Device;
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@ -169,6 +270,7 @@ var
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cmd_list_base : puint32;
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fis_base : puint32;
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cmd_table_base : puint32;
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int_no : uInt8;
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begin
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console.writestringln('AHCI: initilizing a new controller');
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@ -179,11 +281,18 @@ begin
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device := PPCI_Device(ptr);
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pci.enableDevice(device^.bus, device^.slot, device^.func);
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int_no := device^.interrupt_line;
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registerISR(int_no, @ahci_isr);
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controller := PAHCI_Controller(DL_Add(ahciControllers));
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controller^.devices := DL_New(SizeOf(TAHCI_Device));
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controller^.pci_device := PPCI_Device(device);
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// Perform BIOS/OS handoff (if the bit in the extended capabilities is set)
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// Reset controller
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//get the base address of the controller
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page_base := kpalloc(device^.address5); // TODO MEM memory manager need to be improved
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@ -220,6 +329,13 @@ begin
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// exit(true);
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end;
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procedure ahci_isr();
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begin
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console.writestringln('AHCI: ISR');
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//welp there is no way to know what port caused the interrupt or even if it was the controller
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//so we will just have to check all ports, and figure the operation that caused the interrupt
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end;
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end.
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@ -72,7 +72,7 @@ type
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rsv0: uint32; // Reserved
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tfd: uint32; // Task File Data
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signature: uint32; // Signature
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sata_stat: uint32; // SATA Status (SCR0:SStatus)
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sata_status: uint32; // SATA Status (SCR0:SStatus)
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sata_ctrl: uint32; // SATA Control (SCR2:SControl)
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sata_error: uint32; // SATA Error (SCR1:SError)
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sata_active: uint32; // SATA Active
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@ -111,7 +111,7 @@ type
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{
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AHCI Host Bus Adapter (HBA) FIS (Frame Information Structure) Interface
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This structure is used to access the AHCI HBA's FIS (Frame Information Structure)
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memory-mapped registers.
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memory-mapped registers. RX
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}
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THBA_FIS = bitpacked record
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dsfis: array[0..$1F] of uint32; // DMA Setup FIS
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@ -127,15 +127,53 @@ type
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PHBA_FIS = ^THBA_FIS;
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//enum fis type
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TFISType = (
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FIS_TYPE_REG_H2D = $27, // Register FIS - Host to Device
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FIS_TYPE_REG_D2H = $34, // Register FIS - Device to Host
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FIS_TYPE_DMA_ACT = $39, // DMA Activate FIS - Device to Host
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FIS_TYPE_DMA_SETUP = $41, // DMA Setup FIS - Bidirectional
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FIS_TYPE_DATA = $46, // Data FIS - Bidirectional
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FIS_TYPE_BIST = $58, // BIST Activate FIS - Bidirectional
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FIS_TYPE_PIO_SETUP = $5F, // PIO Setup FIS - Device to Host
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FIS_TYPE_DEV_BITS = $A1 // Set Device Bits FIS - Device to Host
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);
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{
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AHCI Host Bus Adapter (HBA) FIS (Frame Information Structure) Interface
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This structure is used to access the AHCI HBA's FIS (Frame Information Structure)
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}
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THBA_FIS_REG_H2D = bitpacked record
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fis_type: uint8; // FIS Type
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pmport: uint8; // Port Multiplier Port
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command: uint8; // Command
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featurel: uint8; // Feature Lower 8-bits
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lba0: uint8; // LBA0
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lba1: uint8; // LBA1
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lba2: uint8; // LBA2
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device: uint8; // Device
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lba3: uint8; // LBA3
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lba4: uint8; // LBA4
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lba5: uint8; // LBA5
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featureh: uint8; // Feature Upper 8-bits
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countl: uint8; // Count Lower 8-bits
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counth: uint8; // Count Upper 8-bits
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icc: uint8; // Isochronous Command Completion
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control: uint8; // Control
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rsv0: array[0..2] of uint8;
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end;
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PHBA_FIS_REG_H2D = ^THBA_FIS_REG_H2D;
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{
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AHCI Host Bus Adapter (HBA) Command Header Interface
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This structure is used to access the AHCI HBA's Command Header memory-mapped
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registers.
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}
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THBA_CMD_HEADER = bitpacked record
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cmd_fis_length: uint8; // Command FIS Length
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atapi: uint8; // ATAPI
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write: uint8; // Write
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wrt: uint8; // Write
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prefetchable: uint8; // Prefetchable
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reset: uint8; // Reset
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bist: uint8; // BIST
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@ -152,14 +190,28 @@ type
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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This structure is used to access the AHCI HBA's Command Table memory-mapped
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registers. The AHCI HBA's Command Table memory-mapped registers are used to
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configure the HBA and to issue commands to the SATA devices connected to the HBA.
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}
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THBA_PRD = bitpacked record
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dba: uint32; // Data Base Address
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dbau: uint32; // Data Base Address Upper 32-bits
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rsv0: uint32; // Reserved
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reserved: ubit9; // Reserved
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dbc: ubit22; // Data Byte Count
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int: ubit1; // Interrupt
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// dbc: uint32; // Data Byte Count, bit 1 is Interrupt, then 22 bits of Byte Count, then 9 bits of Reserved
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end;
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TPRDT = array[0..31] of THBA_PRD;
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PPRDT = ^TPRDT;
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{
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AHCI Host Bus Adapter (HBA) Command Table Interface
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}
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THBA_CMD_TABLE = bitpacked record
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cmd_fis: THBA_FIS; // Command FIS
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acmd: array[0..$1F] of uint8; // ATAPI Command
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rsv0: array[0..$30] of uint8;
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cmd_fis: array[0..63] of uint8; // Command FIS
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acmd: array[0..15] of uint8; // ATAPI Command
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rsv0: array[0..47] of uint8;
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prdt: TPRDT; // Physical Region Descriptor Table
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end;
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PHBA_CMD_TABLE = ^THBA_CMD_TABLE;
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@ -167,42 +219,6 @@ type
|
||||
TCMD_LIST = array[0..255] of THBA_CMD_HEADER;
|
||||
PCMD_LIST = ^TCMD_LIST;
|
||||
|
||||
{
|
||||
AHCI Host Bus Adapter (HBA) Command Table Interface
|
||||
This structure is used to access the AHCI HBA's Command Table memory-mapped
|
||||
registers.
|
||||
}
|
||||
THBA_PRD = bitpacked record
|
||||
dba: uint32; // Data Base Address
|
||||
dbau: uint32; // Data Base Address Upper 32-bits
|
||||
rsv0: uint32; // Reserved
|
||||
dbc: uint32; // Data Byte Count
|
||||
rsv1: uint32; // Reserved
|
||||
end;
|
||||
|
||||
{
|
||||
AHCI Host Bus Adapter (HBA) Command Table Interface
|
||||
This structure is used to access the AHCI HBA's Command Table memory-mapped
|
||||
registers.
|
||||
}
|
||||
THBA_CMD = bitpacked record
|
||||
header: THBA_CMD_HEADER; // Command Header
|
||||
table: THBA_CMD_TABLE; // Command Table
|
||||
prd: array[0..31] of THBA_PRD; // Physical Region Descriptor Table
|
||||
end;
|
||||
|
||||
{
|
||||
AHCI Host Bus Adapter (HBA) Command Table Interface
|
||||
This structure is used to access the AHCI HBA's Command Table memory-mapped
|
||||
registers.
|
||||
}
|
||||
THBA = bitpacked record
|
||||
memory: THBA_Memory; // HBA Memory
|
||||
cmd: array[0..$7FF] of THBA_CMD; // Command List
|
||||
end;
|
||||
|
||||
PHBA = ^THBA;
|
||||
|
||||
//////////////////////////////////////////
|
||||
//////////// Asuro AHCI types ////////////
|
||||
//////////////////////////////////////////
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user