feature: add architecture-agnostic kernel panic (BSOD) engine #57

Merged
admin merged 1 commits from feature/panic into develop 2026-03-08 17:21:44 +00:00
Owner

Introduce core.panic, a new architecture-agnostic kernel panic engine
with a pre-allocated LVGL BSOD screen. The screen and all widgets are
created at init time so that zero LVGL allocation occurs at panic time.

Layout features:

  • Top banner with decoded teapot TGA image (128x128) and title/subtitle
  • Two-column content area with dark semi-transparent cards:
    • Left: Fault Details, CPU Registers, Process Info, System Info
    • Right: Call Stack (full height)
  • Pastel red background (#7A2828), monospace text for data sections

Key changes:

  • Add core.panic.pas with pre-built BSOD screen, register/trace/system
    info formatting, hex conversion helpers, and syslog fallback
  • Add arch.x86.panic.pas as the x86 bridge: packs interrupt registers
    into a TRegisterSnapshot and calls core.panic.panic()
  • Simplify all 19 x86 fault handlers to one-liner panic calls
  • Remove legacy BSOD code from arch.x86.util.pas
  • Add teapot.tga (256x256) embedded via splash_tga.asm
  • Add LVGL bindings: lv_refr_now, lv_image_create, lv_image_set_src,
    lv_image_set_scale, lv_image_set_inner_align, and style helpers
  • Wire up panic init and test command in asuro.pas
Introduce core.panic, a new architecture-agnostic kernel panic engine with a pre-allocated LVGL BSOD screen. The screen and all widgets are created at init time so that zero LVGL allocation occurs at panic time. Layout features: - Top banner with decoded teapot TGA image (128x128) and title/subtitle - Two-column content area with dark semi-transparent cards: - Left: Fault Details, CPU Registers, Process Info, System Info - Right: Call Stack (full height) - Pastel red background (#7A2828), monospace text for data sections Key changes: - Add core.panic.pas with pre-built BSOD screen, register/trace/system info formatting, hex conversion helpers, and syslog fallback - Add arch.x86.panic.pas as the x86 bridge: packs interrupt registers into a TRegisterSnapshot and calls core.panic.panic() - Simplify all 19 x86 fault handlers to one-liner panic calls - Remove legacy BSOD code from arch.x86.util.pas - Add teapot.tga (256x256) embedded via splash_tga.asm - Add LVGL bindings: lv_refr_now, lv_image_create, lv_image_set_src, lv_image_set_scale, lv_image_set_inner_align, and style helpers - Wire up panic init and test command in asuro.pas
admin added this to the 2.0.0 milestone 2026-03-08 17:01:16 +00:00
t3hn3rd was assigned by admin 2026-03-08 17:01:16 +00:00
admin added 1 commit 2026-03-08 17:01:17 +00:00
feature: add architecture-agnostic kernel panic (BSOD) engine
continuous-integration/drone/pr Build is passing
continuous-integration/drone/push Build is passing
e55da49900
Introduce core.panic, a new architecture-agnostic kernel panic engine
with a pre-allocated LVGL BSOD screen. The screen and all widgets are
created at init time so that zero LVGL allocation occurs at panic time.

Layout features:
- Top banner with decoded teapot TGA image (128x128) and title/subtitle
- Two-column content area with dark semi-transparent cards:
  - Left: Fault Details, CPU Registers, Process Info, System Info
  - Right: Call Stack (full height)
- Pastel red background (#7A2828), monospace text for data sections

Key changes:
- Add core.panic.pas with pre-built BSOD screen, register/trace/system
  info formatting, hex conversion helpers, and syslog fallback
- Add arch.x86.panic.pas as the x86 bridge: packs interrupt registers
  into a TRegisterSnapshot and calls core.panic.panic()
- Simplify all 19 x86 fault handlers to one-liner panic calls
- Remove legacy BSOD code from arch.x86.util.pas
- Add teapot.tga (256x256) embedded via splash_tga.asm
- Add LVGL bindings: lv_refr_now, lv_image_create, lv_image_set_src,
  lv_image_set_scale, lv_image_set_inner_align, and style helpers
- Wire up panic init and test command in asuro.pas
Aaron approved these changes 2026-03-08 17:03:50 +00:00
admin merged commit 63b67f5878 into develop 2026-03-08 17:21:44 +00:00
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